Motorola Corporation

Amida Technology Solutions, Inc.

Verigy (singapore) Pte. Ltd.

Silicon Aid Solutions, Inc.

Other

Asset Intertech, Inc.

Southern Methodist University

Advantest (singapore) Pte Ltd

Dafca, Inc.

Alfred Larry Crouch

Matthew D Pressly

Peter Lawrence Levin

Richard C Dokken

John C Potter

Clark Gilson Shepard

Maria Anne Spasojevic

John David Akin

Adam Wade Ley

James M Johnson

Matthew McKinnon Ritonia

Wesley Layton Ellington

Juan Guillermo Revilla

Grady L Giles

Bernard J Pappert

Gerald Chan

Stephen A Cannon

Gary A Winblad

Joseph Charles Circello

James G Gay

Donald L Tietjen

Ruey J Yu

Teresa Louise McLaurin

Jeffrey Freeman

Daniel T Marquette

Peter Levin

Kristen L Mason

Jennifer Lynn Dworak

Michael Alan Mateja

Richard Duerden

Jacob Joseph Orbon, Jr

Pamela S Laakso

Jason E Doege

Lee Allen Corley

Odis Dale Amason, Jr

Jennifer Lynn McKeown

Robert Ash

Paul A Bradley

Gregory Dean Young

Bahram Pouya

Adam Zygmontowicz

Eve Naomi Hunter

A hardware trojan security system may perform a computer implemented method to secure an electronic facility in relation to a hardware trojan, by performing a trojan vulnerability analysis, locating an instrument site location, identifying a selected instrument in relation to an effect of the trojan, marking instrument control-side markers and instrument operative-side markers, marking facility model control-side markers and facility model operative-side markers, marking access architecture control-side markers, and connecting the instrument with the facility model and access architecture by matching corresponding markers.

Method and system for insertion of cybersecurity and hardware assurance instruments within intergrated circuits and electronic systems using multi-stage hardware marking

A method and system for analysis of a facility may include providing an emulation host system, first generating a golden circuit model on the emulation host system, first inserting a first hardware trojan model, first emulating operation of the golden circuit model, and second emulating operation of the first hardware trojan model. A facility may include a trojan instrument facility having a trojan detection instrument comparing logic circuit output against a threshold for detecting hardware trojan activity, and outputting alert data, and in relation to opening one of a plurality of scannable access points, a scannable register is inserted into an active scan chain with an associated instrument interface.

Method, system, and apparatus for security assurance, protection, monitoring and analysis of integrated circuits and electronic systems in relation to hardware trojans

A method and system for analysis of a facility may include providing an emulation host system, generating a pristine circuit model on the emulation host system, inserting a first hardware trojan model, emulating operation of the golden circuit model, and emulating operation of the first hardware trojan model, and determine a set of machine-learning models, detecting the presence of an unknown trojan as a function of the set of machine learning models.

Method, system, and apparatus for security assurance, protection, monitoring and analysis of integrated circuits and electronic systems using machine learning instruments and machine learning analysis

A network of storage units has a data path, which is at least a portion of the network. The network also has a dynamic time-varying or cycle-varying code generation unit and a code comparator unit that together make up an unlock signal generation unit; and a gateway storage unit. If the gateway storage unit does not store an unlock signal or the unlock signal generation unit does not generate and transmit an unlock signal, the gateway storage unit does not insert a data path segment in the data path. If the unlock signal generation unit is operated such that it generates an unlock signal, and it transmits that unlock signal to a gateway storage unit, and the gateway storage unit stores the unlock signal value, then the gateway storage unit inserts a data path segment into the data path.

Using embedded time-varying code generator to provide secure access to embedded content in an on-chip access architecture

Method, system and apparatus for security assurance, protection, monitoring and analysis of integrated circuits and electronic systems in relation to hardware trojans

Using embedded time-varying code generator to provide secure access to embedded content in an on chip access architecture

A method and system for analysis of a facility may include providing an emulation host system, generating a pristine circuit model on the emulation host system, inserting a first hardware trojan model, emulating operation of the golden circuit model, and emulating operation of the first hardware trojan model, and determine a set of machine-learning models, detecting the presence of an unknown trojan as a function of the set of machine learning models and using the same to authenticate the integrity of a GPS signal.

Method, system, and apparatus for verification of operation using GPS receiver input within integrated circuits and electronic systems using an operation navigation system

A method and system for analysis of a facility may include providing an emulation host system, first generating a golden circuit model on the emulation host system, first inserting a first hardware trojan model, first emulating operation of the golden circuit model, and second emulating operation of the first hardware trojan model. The method includes the application of operative vectors to a golden model in simulation or emulation with support of embedded activity monitors to identify which modules contribute to a given functional operation as a method to identify where trojan attacks can be placed.

Method and system for selection of location for placement of trojans, triggers and instruments within integrated circuits and electronic systems using contributory operation analysis

A method and system for analysis of an electronic facility may include providing a mathematical analysis using a scoring system to make generalization about a design and select locations for placement of trojans, triggers and trojan detection instruments within an electronic facility. Such mathematical analysis may include Controllability-Observability analysis as applied to trojan insertion and attacks, and trojan detection instruments.

Method and system for selection of location for placement of trojans, triggers and instruments within integrated circuits and electronic systems using weighted controllability and observability analysis

Various integrated circuits protect hidden content e.g., embedded instruments, keys, data, etc.) using scan cell circuit(s). For example, a first scan cell circuit is connected to the hidden content, and a second scan cell circuit is connected to the first scan cell circuit forming all or part of a serial data path. The first scan cell circuit provides access to the hidden content whenever the first scan cell circuit is in a first specified state and prevents access whenever the first scan cell circuit is in a different state. The first scan cell circuit does not interrupt the serial data path when the first scan cell circuit is in the different state. The second scan cell circuit changes an operational characteristic of the first scan cell circuit whenever the second scan cell circuit is in a second specified state. In some cases, the second scan cell circuit can be eliminated.

Protecting hidden content in integrated circuits

A network of storage units has a data path which is at least a portion of the network. The network also has a key storage unit and a gateway storage unit. If the key storage unit stores a key value, the key storage unit transmits a key signal to the gateway storage unit. If the gateway storage unit does not store a gateway value or the key signal is not transmitted to the gateway storage unit, the gateway storage unit does not insert a data path segment in the data path. If the gateway storage unit stores a gateway value and the key signal is transmitted to the gateway storage unit, the gateway storage unit inserts the data path segment.

Protection of proprietary embedded instruments

A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.

Process for improving design-limited yield by localizing potential faults from production test data

A method for operating a secure semiconductor IP access server to support failure analysis. A client presents a test failure and failure type to an automated server which traverses an electronic product design, definition, and test database to report specifically those components and interconnect likely to cause the failure with geometrical information which may be displayed on the client. Other aspects of semiconductor IP are protected by the server by limiting the trace mechanism and renaming components.

Method for operating a secure semiconductor IP server to support failure analysis

Growing community of inventors

Cedar Park, TX, United States of America

Alfred Larry Crouch