Texas Instruments Corporation

William Marsh Rice University

Alfred J Griffin, Jr

John Paul Campbell

Adel El Sayed

Clint Montgomery

Lin Li

Brian Keith Kirkpatrick

Kelly Jay Taylor

Asad Mahmood Haider

Antonietta Oliva

Joe G Tran

He Lin

Stephen Arlon Meisner

Lee Alan Stringer

Franz R Brotzen

Neel A Bhatt

Lisa A Fritz

Haining S Yang

Daniel L Callahan

Charles Leighton

Methods for removing contaminants from a semiconductor device that includes a plurality of aluminum-comprising bond pads on a semiconductor surface of a substrate. A plurality of aluminum-including bond pads are formed on the semiconductor surface of the substrate. A patterned passivation layer is then formed on the semiconductor surface, wherein the patterned passivation layer provides an exposed area for the plurality of bond pads. Wet etching with a basic etch solution is used to etch a surface of the exposed area of the aluminum-including bond pads, wherein the wet etching removes at least 100 Angstroms from the surface of the bond pads to form a cleaned surface.

Methods for removing contaminants from aluminum-comprising bond pads and integrated circuits therefrom

Defects in components in ICs which may cause circuit failures during operation of the IC are often difficult to detect during and immediately after fabrication of the IC by DC test methods. A method of testing components to detect such defects using AC Impedance Spectroscopy is disclosed. Data may be analyzed using Nyquist plots and Bode plots. Nyquist plots of typical defect types are disclosed. Components may include MOS transistor gate structures, contacts, vias and metal interconnect lines. Components tested may be contained in integrated circuits or in test circuits. Integrated circuits containing components tested by AC Impedance Spectroscopy may be partially fabricated or deprocessed after fabrication.

AC impedance spectroscopy testing of electrical parametric structures

A system () removes wafer edge residue from a target wafer (). A wafer holding mechanism () holds and rotates the target wafer (). A residue remover mechanism () mechanically interacts or abrades an edge surface of the target wafer () and removes strongly adhered residue from the edge surface of the target wafer (). The residue remover mechanism () controls coverage of the mechanical interaction and magnitude of the mechanical interaction.

Systems and methods for removing wafer edge residue and debris using a residue remover mechanism

The present invention provides a method of forming a interconnect barrier layer. In the method, physical vapor deposition of barrier materialis performed within an openinglocated in a dielectric layerof a substrate. RF plasma etching of the barrier materialthat is deposited in the openingoccurs simultaneously with conducting the physical vapor deposition of the barrier material

Simultaneous deposition and etch process for barrier layer formation in microelectronic device interconnects

A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.

Method for forming a void free via

A process whereby elimination of metal extrusion through the via-barrier layer into the base of etched via holes is accomplished by controlling the process temperature of the via-barrier deposition to less than 400&deg; C., and preferably to about 380&deg; C. By eliminating the cause of metal extrusions, i.e., excessive thermally induced stresses on the metal confined biaxially by the dielectric via walls, the resulting defect-free vias are independent of the barrier thickness. The method is applicable to different metal stacks, and in turn, yield and reliability of the device is significantly enhanced.

Method for forming a metal extrusion free via

A electrostatic adhesion tester for thin film conductors. In one embodiment, a device is provided for testing the adhesion strength of a thin film conductor that has been formed upon a substrate. The device includes an adhesion tester that is primarily comprised of a conducting portion. The conducting portion is applied to the thin film conductor so that it does not physically contact the thin film conductor, but leaves a small space there between. A power supply may further be provided for coupling to either the adhesion tester, the thin film conductor, or both in order to create a potential difference between the conducting portion and the thin film conductor. The potential difference creates an electric field between the conducting portion and the thin film conductor that induces stress in the thin film conductor. A measuring device may also be provided for coupling to the adhesion tester and the thin film conductor in order to measure an electrical parameter of the electric field, which is indicative of the adhesion strength.

Electrostatic adhesion tester for thin film conductors

Growing community of inventors

Dallas, TX, United States of America

Alfred J Griffin, Jr