Digital Equipment Corporation

Alfred J Dellicicchi

William F Bruckert

Barbara H Altman

John C Manton

A data handling system for transferring data between two units, the data being transferred in blocks of a selected number of data words, up to predetermined maximum number. A buffer stores the data being transferred. The buffer includes a plurality of stages arranged serially from an input end to an output end, the number of stages being equal in number to the predetermined maximum number of data words that may be transferred in a block. If the number of data words being transferred is less than the predetermined maximum number, as indicated by a control signal from the unit transmitting the data, the buffer either receives the data in the stage a number of stages from the output end, or transmits the data from the stage a number of stages from the input end, equal to the number of words being transferred in the block.

Adjustable buffer for data communications in a data processing system

A memory for use in a digital data processing system, the memory including a memory controller and one or more memory arrays. A memory array performs refresh operations transparently to the memory controller, but in synchronization with a system timing signal while it is receiving normal system power. A memory array also includes asynchronous refresh circuitry for controlling refresh while the system power is interrupted and the array receives no system timing signal. When each refresh operation occurs during power interruption, the asynchronous refresh circuitry tests the condition of the system power supply. Since refresh operations are transparent to the memory controller, the memory array indicates when the memory operations are completed. If the memory operation is a read operation, the memory controller then controls the transfer of data from the array to the controller.

Memory for a digital data processing system including circuit for

In a data processing system, a memory (32) consists of data words and associated error-correction codes that are independently accessible; it is possible simultaneously to read a data word and write its associated error-correction code. This allows a memory-control circuit (30) immediately to store in the memory (32) a data word sent by a processor (10) while it is concurrently in the process of generating the error-correction code for that data word. The result is that the memory-control circuit (30) can subsequently fetch the newly stored data word before storage of its associated error-correction code is complete. This reduces delays involved in error-correction-code generation. The data word includes not only non-redundant information but also parity bits that both the processor (10) and the memory-control circuit (30) employ to determine whether a data word is correct. If the memory-control circuitry (30) determines that a word that it has forwarded to the processor (10) is incorrect, it immediately fetches the corresponding error-correction code and corrects the location in memory. Then, when the processor (10) finds that the parity is incorrect in the data word, it repeats its request for the data word in question, which the memory-control circuit (30) has corrected in the memory (32).

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Acton, MA, United States of America

Alfred J Dellicicchi