Lucent Technologies Inc.

At&t Bell Laboratories

At+t Corp.

Agere Systems Inc.

Lattice Semiconductor Corporation

American Telephone & Telegraph Co., At&t Bell Laboratories

Agere Systems Guardian Corp.

Dafca, Inc.

Alfred E Dunlop

Thaddeus John Gabara

Wilhelm Carl Fischer

Dusan Suvakovic

Scott C Knauer

Doutje T Van Veen

Mihai Banu

Glenn M Boles

John P Fishburn

Manyalibo Joseph Matthews

William B Andrews

Miron Abramovici

Harold Scholz

Yusuke Ota

Ilija Hadzic

Asawaree P Kalavade

Kalpendu Ranjitrai Shastri

Brian W Kernighan

A method and apparatus for clock and data recovery that is advantageous in burst-mode systems is disclosed. This clock and data recovery method allows a) fast locking to a rapidly changed phase of the transmission clock, and b) stable tracking of a slowly changing phase of the transmission clock. Such fast locking minimizes the 'guard band' between consecutive transmission bursts, while stable tracking provides reliable data tracking, resulting in the efficient use of bandwidth. A plurality of clock signals, is generated, each having a different phase. The phase of an input signal data stream is determined and a desired clock signal in the plurality that corresponds to the phase of the input data stream is selected and used to sample the input signal data stream.

Method and apparatus for multiphase, fast-locking clock and data recovery

A clock recovery method is disclosed wherein the FIFO delay of data words and the phase difference between a data word and a receiver clock are used to time data transmissions from a transmitter. The phase difference between the data word and the receiver clock is determined by the offset of a word relative to a desired position in a storage buffer. The FIFO delay is determined either by measuring the difference between a read pointer and a write pointer in the FIFO or, alternatively, by calculating the difference between a timestamp of the time a data word entered the FIFO and the current time as the data word is read from the FIFO.

Clock, data and time recovery using bit-resolved timing registers

An exceptionally effective SoC design is achieved by the user of wrappers that comprise a functionally reconfigurable module (FRM) that is capable of affecting the operational functionality of the wrapper and that, consequently, is capable of affecting the operational functionality of a designed SoC. One embodiment of a core+wrapper combination comprises distinct input and output cells within the wrapper, and a separate FRM. Another embodiment may embed the input and output cells within the FRM. The FRM may be implemented with, for example, a field programmable logic array (FPLA). An additional advance is realized by providing a number of spare leads in the signal paths network that interconnects the various SoC elements.

Reconfigurable fabric for SoCs using functional I/O leads

A gated clock recovery circuit is disclosed that receives an input data stream and generates a frequency and phase aligned clock output. The gated clock recovery circuit substantially instantaneously adjusts the generated clock signal to phase changes in the incoming data stream. In addition, the gated clock recovery circuit generates the clock output signal using only transmitted non-predetermined data. The gated clock recovery circuit includes two PLL circuits. The first PLL (PLL) adjusts to the frequency of the transmitter, and provides a bias voltage, CAP, to the second PLL (PLL) to indirectly initially tune the second PLL. The bias voltage, CAP, is applied to the second PLL through a transmission gate (or switch) that is initially in a closed (short) position. Thus, the first PLL drives the bias voltage, CAP, of the second PLL, to align the frequency with the transmitter, until received data opens the transmission gate. Thereafter, the bias voltage, CAP, is removed and the second PLL can operate without being controlled by PLLso that the second PLL oscillates in phase with the received data. Simultaneously, the received data starts the oscillator in the second PLL so that the second oscillator is in phase with the received data. The second PLL then maintains this phase relationship between the second oscillator and the received data.

Gated clock recovery circuit

A network interface architecture includes a processor having an associated program memory, and a programmable logic device coupled to the processor. A connection port of the logic device is adapted to be coupled to a medium of a selected network having a defined network protocol, and the logic device has an associated configuration memory. A data communication path is coupled to the processor and the logic device, and is arranged to connect with a host device for transferring data between the host device and a network to which the logic device is coupled. The processor responds to information identifying a selected network by loading corresponding network protocol data from the configuration memory and the program memory into the logic device and the processor. The host device may include, without limitation, a personal, lap top, desk top or hand-held computer, a network appliance, file server, printer, vending machine, cell phone or the like.

Reconfigurable network interface architecture

Fractional cycle stealing units are introduced in the routing of a programmable device such as an FPGA or FPSC to increase system performance resulting from the particular clock routing. The disclosed fractional cycle stealing units enable given amounts of clock skew between individual distribution sinks, and/or between logic paths that are in series. Each of the delay elements 'steals' a portion of a clock cycle (and perhaps one or more full clock cycles) from subsequent circuits to provide a more reliable logical function, and to avoid the need for overall additional clock cycles. These fractional cycle stealing elements offer a signal skew adjustment at the sinks of the distribution with no additional routing congestion expense. The disclosed cycle stealing delay elements are programmable, and enable clock skew between individual distribution sinks.

Signal distribution scheme in field programmable gate array (FPGA) or field programmable system chip (FPSC) including cycle stealing units

The clock may be recovered rapidly for burst mode signals that are at one of a set of different a priority known frequencies by using a single device that is similar to that of U.S. Pat. No. 5,237,290 except that the delay lines used in each of the gated oscillators are controllably selectable so that the gated oscillators are each capable of providing a clock signal at more than one frequency. Typically, the same frequency is selected for use by both of the gated oscillators at any one time. This is achieved by having each gated oscillator be made up of 1) a plurality of &ldquo;internal&rdquo; gated oscillators that each have different length delay lines, and 2) a selector for selecting the output of one of the internal gated oscillators that is to be used for a particular frequency. The internal gated oscillators may be made up of delay elements. The ratio of the number of delay elements in the various internal gated oscillators to each other determines their relative frequency. When the delay elements that make up the internal gated oscillators are inverters, a phase splitter may be employed to insure that the number of delay elements effectively remains odd to insure that oscillation takes place even when a ratio of two in the frequencies recovered is required.

Clock recovery from a burst-mode digital signal each packet of which may have one of several predefined frequencies

A clock recovery circuit is coupled to an elastic storage circuit such as a FIFO circuit. More specifically, a first input of the elastic storage circuit is electrically connected to an output of the clock recovery circuit. A second input for accepts a data signal representing an input data stream from a communications medium. A third input accepts a local clock signal. The resultant circuit may be used in receiver's for communications systems to help alleviate the problems of frequency mismatch and jitter.

Clock recovery circuit

The output frequency of a simple low-power-dissipation oscillator circuit designed to drive PPS CMOS circuits is controlled by a closed-loop system. In response to deviations of the output frequency from a prescribed value, the system generates correction signals that are applied to an array of capacitors. In that way, capacitance is electrically added to or subtracted from a series-resonant path of the oscillator circuit, thereby to automatically establish and maintain the output frequency of the circuit at or near its prescribed value.

Closed-loop frequency control of an oscillator circuit

Effective control of impedance values in integrated circuit applications is achieved with an integrated circuit transistor whose size is digitally controlled. The digitally controlled size is achieved, for example, with a parallel interconnection of MOS transistors. In one application, the digitally controlled transistor serves as a controlled impedance connected to an output terminal of an integrated circuit. In that application, a number of transistors are enabled with control signals, and the collection of enabled transistors is responsive to the input signal that normally is applied to a conventional transistor. In another application, where the digitally controlled transistor serves as a controlled impedance at the input of a circuit, only the control signals that enable transistors and thereby determine the effective developed impedance are employed. In still another application, the digital control of the transistor's size is employed to control the speed or power consumption of the effective transistor. Such control is exercised to erase the manufacturing variability of the integrated circuit. Alternatively, such control is exercised as part of a feedback control of the operational characteristics of the entire circuit. In the feedback control application, the digital signals that control the transistor's size are obtained from an assessment of the circuit's operation. In the manufacturing variability control application, the digital signals that control the transistor's size are obtained from a measure of the integrated circuit's parameters relative to a reference element.

Digitally controlled element sizing

A method and apparatus for recovering the phase of a signal which may change at periodic intervals is disclosed which comprises gated variable frequency oscillators. These results are obtained in an illustrative embodiment of the present invention in which an incoming signal is fed into a gated oscillator and the complement of the incoming signal is fed into a matching gated oscillator. Advantageously, the respective outputs of the two oscillators are fed into a Boolean NOR gate. When the gated oscillators are designed to oscillate at the frequency of the incoming signal, the output waveform will have a bounded phase relationship with respect to the incoming signal.

Method and apparatus for clock recovery

Effective control of impedance values in integrated circuit applications is achieved with an integrated circuit transistor whose size is digitally controlled. The digitally controlled size is achieved, for example, with a parallel interconnection of MOS transistors. In one application, the digitally controlled transitor serves as a controlled impedance connected to an output terminal of an integrated circuit. In that application, a number of transistors are enabled with control signals, and the collection of enabled transistors is responsive to the input signal that normally is applied to a conventional transistor. In another application, where the digitally controlled transistor serves as a controlled impedance at the input of a circuit, only the control signals that enable transistors and thereby determine the effective developed impedance are employed. In still another application, the digital control of the transistor's size is employed to control the speed or power consumption of the effective transistor. Such control is exercised to erase the manufacturing variability of the integrated circuit. Alternatively, such control is exercised as part of a feedback control of the operational characteristics of the entire circuit. In the feedback control application, the digital signals that control the transistor's size are obtained from an assessment of the circuit's operation. In the manufacturing variability control application, the digital signals that control the transistor's size are obtained from a measure of the integrated circuit's parameters relative to a reference element.

A method and system for improving the design of an integrated circuit by iteratively analyzing the circuit and improving it with each iteration, until a preselected constraint is met. The design improvement is realized by selecting a model for the delay through each active element of the circuit that is characterized by a convex-function of the logarithm of the active element's size. Using the convex function model, with each iteration a static timing analysis of the circuit identifies the output that most grievously violates the specified constraint. With that output selected, an analysis of the path's timing structure identifies the active element in that path whose change in size would yield the largest improvement in performance. The size of that active element is adjusted accordingly and the iteration is repeated. For further improvement, the interconnection pattern of subnetworks of the circuit is evaluated and rearranged to improve performance.

Transistor sizing system for integrated circuits

In laying out integrated circuits on a substrate, the placement of the components relative to each other is important in minimizing conductor area and hence chip area. Large scale integration often uses polycells which are lined up in rows to realize the digital logic circuitry. A partitioning procedure is disclosed which iteratively separates the cells into maximally connected subcells, eventually to assign them to rows so as to minimize conductor area. A technique called terminal propagation takes into account at every iteration the location of connections outside of the partitioned area. Rectilinear Steiner trees are generated to aid in terminal propagation.

Growing community of inventors

Murray Hill, NJ, United States of America

Alfred E Dunlop