Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Micron Technology Incorporated

Alfonso Maurelli

Paolo Giuseppe Cappelletti

Paola Zabberoni

Carlo Riva

Paolo Ghezzi

Nicola Zatelli

Daniela Peschiaroli

Fausto Piazza

Livio Baldi

Elisabetta Palumbo

Rino Micheloni

Giovanni Campardo

Emilio Camerlenghi

Marco Olivo

Danilo Re

Loris Vendrame

Paolo Colombo

Massimo Ati

Different types of transistors, such as memory cells, higher voltage, and higher performance transistors, may be formed on the same substrate. A transistor may be formed with a first polysilicon layer covered by a dielectric. A second polysilicon layer over the dielectric may be etched to form a sidewall spacer on the gate of the transistor. The sidewall spacer may be used to form sources and drains and to define sub-lithographic lightly doped drains. After removing the spacer, the underlying dielectric may protect the lightly doped drains.

Integrating diverse transistors on the same wafer

An embodiment of a process is disclosed herein for fabricating a memory device integrated on a semiconductor substrate and comprising at least a nanocrystal memory cell and CMOS transistors respectively formed in a memory area and in a circuitry area. According to an embodiment, a process includes forming a nitride layer having an initial thickness, placed above a nanocrystal layer, in the memory area and the formation in the circuitry area of at least one submicron gate oxide. The process also provides that the initial thickness is such as to allow a complete transformation of the nitride layer into an oxide layer at upon formation of said at least one submicron gate oxide.

Process for manufacturing a memory device integrated on a semiconductor substrate and comprising nanocrystal memory cells and CMOS transistors

A method for sealing electronic devices formed on a semiconductor substrate includes forming a plurality of first electronic devices adjacent a first portion of the semiconductor substrate, with each first electronic device including a first region comprising at least one first conductive layer projecting from the semiconductor substrate. A first sealing layer is formed adjacent the first regions for sealing the plurality of first electronic devices. A protective layer is formed adjacent the first sealing layer. The protective layer is etched to form protective spacers adjacent sidewalls of the first regions. The method further includes forming a plurality of second electronic devices adjacent a second portion of the semiconductor substrate, with each second electronic device including a second region comprising a second conductive layer projecting from the semiconductor substrate. A second sealing layer is formed adjacent the second regions for sealing the plurality of second electronic devices, and adjacent the first sealing layer for sealing the plurality of first electronic devices.

Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure

A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. The inserting includes identifying, among the electrically non-active structures, a first group of electrically non-active structures to be adjacent the first and second electrically active structures, and identifying, among the electrically non-active structures, a second group of electrically non-active structures not adjacent to the first and second electrically active structures. The method further includes defining, on the semiconductor substrate, the first and second groups of electrically non-active structures through different photolithographic steps.

Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit

A test chip performs measurements to evaluate the performances of interconnects. In particular, the statistical failure distribution, the electromigration and the leakage current are measured. An algorithm detects a via failure at any of the available n metal layers. The test chip includes a ROM memory array. The vias to be measured are formed in the columns of the array. Via or contact failures are detected by forcing a predetermined current through both an array column and a reference column. The failure analysis is obtained by comparing the resulting voltage drops.

Analysis of the quality of contacts and vias in multi-metal fabrication processes of semiconductor devices, method and test chip architecture

A method for sealing electronic devices formed on a semiconductor substrate includes forming at least one first conductive layer on a first portion of the semiconductor substrate for defining electronic devices, and forming a second conductive layer on a second portion of semiconductor substrate for also defining electronic devices. First regions are formed in the at least one first conductive layer for defining electronic devices, and a first sealing layer is formed on the whole semiconductor substrate to seal the first regions. Second regions are formed in the second conductive layer for defining electronic devices, and a second sealing layer is formed on the whole semiconductor substrate to seal the second regions.

An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.

Electrically erasable and programmable non-volatile memory cell

A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, forming from a second polysilicon layer control gate electrodes for the memory cells, and gate electrodes for the second transistors; in the first portions of the semiconductor substrate, forming source and drain regions for the first transistors; in the second portions of the semiconductor substrate, forming source and drain regions for the memory cells; in the third portions of the semiconductor substrate, forming source and drain regions for the second transistors.

Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry

The method applies to non-volatile semiconductor memories with cells arranged in rows and in columns, in which each cell has a first terminal, a second terminal, and a third terminal connected, respectively, to a row line, to a column line, and to a common node by respective connection strips. In order to form connections with low resistivity and consequently to save semiconductor area, the method provides for the formation of an oxide layer which covers the connection strips of the first terminals and of the third terminals, the formation of channels along the connection strips until the surfaces thereof are exposed, and the filling of the channels with a material having a resistivity lower than that of the connection strips.

Method of forming low-resistivity connections in non-volatile memories

A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.

Method of manufacturing an integrated circuit, for integrating an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip

The memory cell is of the type with a single level of polysilicon, and comprises a sensing transistor and a select transistor. The sensing transistor comprises a control gate region with a second type of conductivity, formed in a first active region of a substrate of semiconductor material, and a floating gate region which extends transversely relative to the first active region. The control gate region of the sensing transistor is surrounded by a first well with the first type of conductivity, and in turn is surrounded, below and laterally, by a second well with the second type of conductivity, thus forming a triple-well structure. A second triple-well structure can be formed in a second active region adjacent to the first active region, and can accommodate conduction regions of the sensing transistor and of the select transistor.

EEPROM type non-volatile memory cell and corresponding production method

Method of manufacturing an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip

A method of forming a doped region in an integrated circuit which includes a matrix of memory cells and lightly-doped drain transistors and which is fabricated by means of a process providing for a Self-Aligned Source masked etch and implant and for a selective salicidation of some doped regions, the doped region suitable for forming an integrated resistor and/or an abrupt-profile source/drain region of a transistor. The doped region is formed by introducing into a semiconductor layer of a first conductivity type a dopant of a second conductivity type and exploiting the SAS masked implant used to form source regions of the matrix of memory cells. At least a portion of a surface of the doped region is prevented from being salicidated by using as a protective mask a portion of a dielectric layer from which insulating sidewall spacers for the LDD transistors are formed.

METHOD FOR THE INTEGRATION OF RESISTORS AND ESD SELF-PROTECTED TRANSISTORS IN AN INTEGRATED DEVICE WITH A MEMORY MATRIX MANUFACTURED BY MEANS OF A PROCESS FEATURING SELF-ALIGNED SOURCE (SAS) FORMATION AND JUNCTION SALICIDATION

A process for the integration in a semiconductor chip of an integrated circuit including a high-density integrated circuit components portion and a high-performance logic integrated circuit components portion, providing for: over a semiconductor substrate, insulatively placing a silicidated polysilicon layer that includes a polysilicon layer selectively doped in accordance to a conductivity type of at least the high-performance logic integrated circuit components, covered by a silicide layer; selectively covering the silicidated polysilicon layer with a hard mask; defining gate structures for the high-density integrated circuit components and for the high-performance logic integrated circuit components using said hard mask, the gate structures comprising the silicidated polysilicon layer covered with the hard mask; in a dielectric layer formed over the chip, forming contact openings for electrically contacting the high-density integrated circuit components and the high-performance logic integrated circuit components, wherein at least the contact openings for electrically contacting the high-density integrated circuit components are formed in self-alignment with the gate structures thereof.

MANUFACTURING PROCESS FOR THE INTEGRATION IN A SEMICONDUCTOR CHIP OF AN INTEGRATED CIRCUIT INCLUDING A HIGH-DENSITY INTEGRATED CIRCUIT COMPONENTS PORTION AND A HIGH-PERFORMANCE LOGIC INTEGRATED CIRCUIT COMPONENTS PORTION

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Sulbiate, Italy

Alfonso Maurelli