Nxp Usa, Inc.

Freescale Semiconductor,inc.

Broadcom Corporation

Alexis Nathanael Huot-Marchand

Patrice Besse

Christelle Franchini

Jacques Jean Bertin

Joannes Mathilda Josephus Sevenhans

Alain Salles

Guillaume Mouret

Jean-Philippe Laine

Laurent Bordes

Simon Bertrand

Koen Geirnaert

Johan Janssens

Christophe Gouwy

Stefan Van Roeyen

Pascal Kamel Abouda

Jean Philippe Laine

Pascal Sandrez

Matthew Bacchi

Murielle Delage

Stephanie Creveau-Boury

Hamada Ahmed

Matthieu Aribaud

Nicolas Jarrige

Johann Janssens

A switchable termination resistance circuit for a transceiver physical layer interface. Example embodiments include a switchable termination resistance circuit for a transmission line transceiver, the switchable termination resistance circuit comprising: first and second terminals for connection to a transmission line; first and second NMOS termination resistance switches having source connections connected together at a midpoint node and gate connections connected to an input node; a first resistor connected between the first terminal and a drain connection of the first NMOS termination resistance switch; a second resistor connected between the second terminal and a drain connection of the second NMOS termination resistance switch; a Zener diode having a cathode side connected to the input node and an anode side connected to the midpoint node; and a branch comprising a second Zener diode, a branch diode, a branch NMOS switch and a branch PMOS switch in a series connected arrangement between the midpoint node and a ground line.

Switchable termination resistance circuit

A battery management system comprises a first and second battery cell controllers and a transmission line providing a point-to-point signal transmission path between the first and second battery cell controllers. At least one of the first and second battery cell controllers includes a logic circuit constructed and arranged for encoding data for transmission as a serial data stream along the signal transmission path in compliance with a multi-level encoding technique. The logic circuit comprises an encoding/decoding circuit that generates a modulated signal of the serial data stream over at least three discrete signal levels at a predetermined and fixed data pulse frequency for transmission through the transmission line and encodes a plurality of data units of the serial data stream into a data packet. The data packet includes at least three symbols constructed and arranged with at least four consecutive transmissions per symbol. Each transmission of each symbol assumes one of the three discrete signal levels. At least one transceiver is configured in a transmit mode or a receive mode and that discards any combinations of the maximum number of possible combinations to reduce a source of electromagnetic interference (EMI) on the transmission line.

Multi-level encoding for battery management system

A battery management system comprises a first battery cell controller; a second battery cell controller, the first battery cell controller and the second battery cell controller each monitoring a plurality of battery cells; and a galvanically isolated transmission line providing a point-to-point signal transmission path between the first battery cell controller and the second battery cell controller. At least one of the first battery cell controller or the second battery cell controller includes at least one encoding/decoding circuit for encoding data for transmission as a serial data stream along the signal transmission path in compliance with a multi-level encoding technique, including modulating the serial data stream over at least three discrete signal levels at a predetermined and fixed data pulse frequency, encoding a plurality of data nibbles of the serial data stream into a data packet, the data packet including a plurality of symbols constructed and arranged with at least four consecutive chips per symbol, wherein the at least four consecutive chips per symbol of the data packet includes a DC balanced line code in each of the symbols.

Multi-level encoding for battery management system field

An integrated circuit for use in a differential network bus node comprising: a transceiver having a first transceiver input-output terminal and a second transceiver input-output terminal; a physical layer high terminal connected to the first transceiver input-output-terminal; a physical layer low terminal connected to the second transceiver input-output terminal; and a physical layer interface circuit comprising: a first low frequency RC matching circuit and a first high frequency RC matching circuit each connected between the first transceiver input-output-terminal and a first reference terminal; and a second low frequency RC matching circuit and a second high frequency RC matching circuit each connected between the second transceiver input-output terminal and a second reference terminal.

Integrated circuit with physical layer interface circuit

A detector () detects an unwanted oscillation generated by a closed-loop system () due to disconnection, improper usage, or absence of a stability-controlling element () necessary for the closed-loop system to function properly. An integrated circuit () includes the closed-loop system, the detector, and a supervisory system () that disables the closed-loop system upon disconnection of the stability-controlling element from the closed-loop system.

Closed-loop system oscillation detector

A ground-loss detection circuit for an integrated circuit, (IC) device including a first dynamic threshold metal oxide semiconductor (DTMOS) device operably coupled between a first ground plane of the IC device and at least one further ground plane of the IC device, at least one of the first and at least one further ground planes comprising an external ground connection of the IC device, at least one further DTMOS device operably coupled between the first and at least one further ground planes of the IC device in an opposing manner to the first DTMOS device, and at least one ground-loss detection component operably coupled to at least one of the first and at least one further DTMOS devices and arranged to detect a ground-loss for at least one of the first and at least one further ground planes based at least partly on a drain current of the at least one of the first and at least one further DTMOS device(s).

Ground-loss detection circuit

A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad.

Semiconductor device and an integrated circuit comprising an ESD protection device, ESD protection devices and a method of manufacturing the semiconductor device

A homogeneity detection circuit, a valve driving system, a vehicle, an integrated circuit and a method of homogeneity detection in a valve driving system are provided. The homogeneity detection circuit comprises a first input, a second input and a comparison circuit. The first input receives a first signal being related to a first driving signal for driving a first valve. The second input receives a second signal being related to a second driving signal for driving a second valve. The comparison circuit compares the first signal with the second signal and generates a warning signal if predetermined differences are detected between the first driving signal and the second driving signal.

Homogeneity detection circuit, a valve driving system and a method of homogeneity detection in a valve driving system

A method and circuit for controlling current through an inductive load such as an electromagnetic valve of a vehicle anti-lock braking system includes first and second driver stages, controlled by PWM (pulse width modulation) signals, for providing, respectively, an actuation path for valve current in an 'on' phase and a recirculation path for valve current in an 'off' phase. A peak value of current flowing in the actuation path at the end of an &#x201c;on&#x201d; phase is compared with a peak value of current flowing in the recirculation path at the start of the &#x201c;off&#x201d; phase in order to detect any malfunction of the circuit. An embodiment of the invention has the advantage of being able to detect any malfunction at very low and very high PWM duty cycles.

Inductive load control circuit, a braking system for a vehicle and a method of measuring current in an inductive load control circuit

A local area networking apparatus comprises a power stage for connecting to a network cable for carrying power and data. The power stage comprises a main current flow path which includes a switch comprising at least one transistor positioned in the main current flow path and a current monitoring apparatus for monitoring current flow in the main current flow path, and wherein the current monitoring apparatus comprises a sensor which is not placed in series with the main current flow path. The current monitoring apparatus can comprise a current mirroring stage which is arranged to mirror current flowing in the main current flow path to a monitoring current flow path. The switch can be implemented as a set of switches.

Current-monitoring apparatus

A local area networking apparatus comprises a power stage for connecting to a network cable for carrying carry power and data. The power stage comprises a main current flow path which includes a switch comprising at least one transistor positioned in the main current flow path and a current monitoring apparatus for monitoring current flow in the main current flow path, and wherein the current monitoring apparatus comprises a sensor which is not placed in series with the main current flow path. The current monitoring apparatus can comprise a current mirroring stage which is arranged to mirror current flowing in the main current flow path to a monitoring current flow path. The switch can be implemented as a set of switches.

An electrical circuit for manipulating at least one of a voltage and a current on a bus wire comprises a first switch having a first gate, a first source, and a first potential reduction unit. The first potential reduction unit is suitable for lowering a potential difference between the first gate and the first source of the first switch, wherein the lowering of the potential difference is caused by a shutting-off of a first control voltage.

Bus driver for avoiding an overvoltage

A semiconductor device comprises at least one switching element. The at least one switching element comprises a first channel terminal, a second channel terminal and a switching terminal, the switching element being arranged such that an impedance of the switching element between the first and second channel terminals is dependant upon a voltage across the switching terminal and the first channel terminal. The semiconductor device further comprises a resistance element operably coupled between the first channel terminal of the at least one switching element and a reference node, and a clamping structure operably coupled between the switching terminal of the switching element and the reference node. The resistance element and the clamping structure are arranged such that, when current flowing through the at least one switching element, between the first and second channel terminals, exceeds a threshold current value, a voltage drop across the resistance element exceeds a difference between (i) a clamping voltage of the clamping structure and (ii) a switching voltage threshold of the at least one switching element, causing the impedance between the first and second channel terminals of the at least one switching component to increase.

Semiconductor device and method of electrostatic discharge protection therefor

A semiconductor device comprises a switching element. The switching element comprises a first channel terminal, a second channel terminal and a switching terminal. One of the first and second channel terminals provides a reference terminal and the switching element is arranged such that an impedance of the switching element between the first channel terminal and second channel terminal is dependant upon a voltage across the switching terminal and the reference terminal. The semiconductor device further comprises a first resistance element operably coupled between the first channel terminal and the switching terminal and a second resistance element operably coupled between the switching terminal and the second channel terminal of the semiconductor device. When a negative current is encountered at the first channel terminal, the negative current causes both a voltage drop across the switching terminal and the first channel terminal and a voltage drop across the second channel terminal and the switching terminal.

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Labastidette, France

Alexis Nathanael Huot-Marchand