Intel Corporation

Alexey Kukanov

Arch D Robison

Anton Malakhov

Alexandr Konovalov

A method according to one embodiment includes the operations of loading binary code comprising a top level task into memory on a first processor, the top level task having an associated range; determining if the top level task is divisible into a plurality of sub-tasks based on the range; for each of the sub-tasks, determining if a given sub-task is divisible into a plurality of sub-sub-tasks; and if the given sub-task is indivisible, executing the given sub-task; otherwise, if the given sub-task is divisible, dividing the given sub-task into the plurality of sub-sub-tasks.

Method and system for work partitioning between processors with work demand feedback

Embodiments of computer-implemented methods, apparatus and computer-readable media associated with memory management are disclosed herein. A computer-implemented method to coalesce free intervals of a memory may include ascertaining that a first interval of the memory is free (). A determination may be made, e.g., from a header associated with the first interval of the memory, whether a second interval of the memory, immediately preceding or following the first interval of the memory, is free (). After a determination is made that the second interval of the memory is free, the first interval of the memory and the second interval of the memory may be coalesced (). Other embodiments may be described and/or claimed.

Memory coalescing computer-implemented method, system, apparatus and computer-readable media

Implementing fair scalable reader writer mutual exclusion for access to a critical section by a plurality of processing threads is accomplished by creating a first queue node for a first thread, the first queue node representing a request by the first thread to access the critical section; setting at least one pointer within a queue to point to the first queue node, the queue representing at least one thread desiring access to the critical section; waiting until a condition is met, the condition comprising the first queue node having no preceding write requests as indicated by at least one predecessor queue node on the queue; permitting the first thread to enter the critical section in response to the condition being met; and causing the first thread to release a spin lock, the spin lock acquired by a second thread of the plurality of processing threads.

Fair scalable reader-writer mutual exclusion

Implementing fair scalable reader writer mutual exclusion for access to a critical section by a plurality of processing threads in a processing system is accomplished by creating a first queue node for a first thread on the first thread's stack, the queue node representing a request by the first thread to access the critical section; adding the first queue node to a queue pointed to by a single word reader writer mutex for the critical section, the queue representing a list of threads desiring access to the critical section, each queue node in the queue being on a stack of a thread of the plurality of processing threads; waiting until the first queue node has no preceding write requests as indicated by predecessor queue nodes on the queue; entering the critical section by the first thread; exiting the critical section by the first thread; and removing the first queue node from the queue.

Growing community of inventors

Nizhny Novgorod, Russia

Alexey Kukanov