Intel Corporation

Alexey Kostinsky

Nadav Bonen

Kuljit Singh Bains

Christopher P Mozak

Theodore Zale Schoenborn

Christopher E Cox

Nagi Aboulenein

Tomer Levy

James M Shehadi

Paul S Cheses

Danny Naiger

Zvika Greenfield

Pavel Konev

Olga Fomenko

On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.

Programmable on-die termination timing in a multi-rank system

In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.

Interference testing

A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.

On-die termination control without a dedicated pin in a multi-rank system

A system avoids false sampling due to reflections from previous commands or other noise on a data strobe line. The system uses a normalizer circuit or leaker circuit, and the data strobe line is not optimally terminated or is unterminated. The data strobe line is to receive a burst of data sample pulses or edges and sample a data line based on the edges. The receiving device includes logic that generates a count triggered from an initial edge on the data strobe line, and identifies, based on the count, an initial valid edge of the burst. Any false strobes due to noise or reflections that are received prior to the actual burst can be rejected.

Avoiding DQS false sampling triggers

Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping. Varying the transmitted CA patterns and the resulting feedbacks sampled on memory controller data signals allows CA/CTRL/CLK signals delay training with and without priory data pins mapping knowledge.

Training for command/address/control/clock delays under uncertain initial conditions and for mapping swizzled data to command/address signals

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Nahariya, Israel

Alexey Kostinsky