Qualcomm Incorporated

Jiao, Guofang

Alexei Vladimirovich Bourd

Andrew Evan Gruber

Yun Du

Chun Yu

Guofang Jiao

Colin Christopher Sharp

Lin Chen

David Rigel Garcia Garcia

David Kirk McAllister

Gang Zhong

Chihong Zhang

Eric Demers

Fei Wei

Minjie Huang

Yibin Zhang

Vineet Goel

Maxim V Kazakov

Jay Chunsup Yun

Chunhui Mei

Elina Kamenetskaya

Hongjiang Shang

William Torzewski

Jing Han

Shuaib Uddin Arshad

Bohuslav Rychlik

Tao Wang

Avinash Seetharamaiah

Piyush Gupta

Anirudh Rajendra Acharya

Christopher Paul Frascati

Murat Balci

Yang Yu

Swapnil Pradipkumar Sakharshete

Lingjun Chen

Jian Liang

Xiangdong Jin

Milind Nilkanth Nemlekar

Zilin Ying

Angus Dorbie

Sumesh Udayakumaran

Dam Backer

Reza Pourreza Shahri

Pavan Kumar Akkaraju

Robert J Simpson

Brian Ellis

Tzung Ren Tzeng

Francois Mathias Robert Demoullin

Liang Han

Fei Xu

Aleksandra L Krstic

Roman Larionov

Li He

Vaibhav Rajesh Gandhi

Heng Qi

Jiexia Yu

Vladislav Shimanskiy

William F Torzewski

Guofang Jia

Systems and techniques are provided for determining bounding regions for a hierarchical structure for ray tracing. For instance, a process can include obtaining an acceleration data structure, the acceleration data structure including one or more primitives of a scene object. A graph cut can be applied to the acceleration data structure. A set of nodes of the acceleration data structure can be determined based on the graph cut, wherein the determined set of nodes is located adjacent to the graph cut. A world-space bounding box can be generated for the scene object, using the set of nodes determined based on the graph cut.

Generation of tight world space bounding regions

The present disclosure relates to methods and apparatus for graphics processing, e.g., a GPU. The apparatus may receive an image including a plurality of pixels associated with one or more workgroups and one or more pixel tiles, each of the workgroups and the pixel tiles including one or more pixels of the plurality of pixels. The apparatus may determine whether the one or more workgroups are misaligned with the one or more pixel tiles. The apparatus may determine a conversion order of the one or more workgroups when the one or more workgroups are misaligned with the one or more pixel tiles, the conversion order corresponding to a common multiple of one of the one or more workgroups and one of the one or more pixel tiles. The apparatus may convert each of the one or more workgroups based on the conversion order of the one or more workgroups.

Rasterization of compute workloads

Systems and techniques are provided for accelerated ray tracing. For instance, a process can include obtaining a hierarchical acceleration data structure that includes a plurality of primitives of a scene object and obtaining a respective information value associated with each primitive included in the plurality of primitives. A sort order can be determined for two or more nodes included in a same level of the hierarchical acceleration data structure at least in part by sorting the two or more nodes based on a respective sorting parameter value determined for each respective node of the two or more nodes. Each respective sorting parameter value can be determined based on at least one information value associated with one or more primitives included in a sub-tree of each respective node of the two or more nodes. The hierarchical acceleration data structure can be traversed using the sort order.

Accelerated bounding volume hierarchy (BVH) traversal for ray tracing

Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of a BVH structure associated with a view frustum, where the BVH structure includes at least one first-level BVH including a plurality of first-level nodes and a plurality of second-level BVHs including a plurality of second-level nodes. The apparatus may also calculate whether the view frustum intersects with each first-level bounding box in the at least one first-level BVH. Further, the apparatus may calculate, for each first-level bounding box that the view frustum intersects, whether the view frustum intersects with each first-level child nod that is associated with each first-level bounding box. The apparatus may also output an indication of all of the first-level child nodes that the view frustum intersects for each of the set of first-level bounding boxes that the view frustum intersects.

Geometry culling using bounding volume hierarchy (BVH) for ray tracing

The present disclosure relates to methods and apparatus for compute processing. For example, disclosed techniques facilitate improving performance of matrix multiplication in streaming processor. Aspects of the present disclosure can execute, with a load control unit, a first load instruction to load a set of input data of an input matrix from a first memory to a second memory. Aspects of the present disclosure can also execute, with the load control unit, a second load instruction to load a set of weight data of a weight matrix from the first memory to the second memory. Additionally, aspects of the present disclosure can perform, with an ALU component, a matrix multiplication operation using the set of input data and the set of weight data to generate an output matrix. Further, aspects of the present disclosure can store the output matrix at a general purpose register accessible to the ALU component.

Performing matrix multiplication in a streaming processor

Systems and techniques are provided for enhancing operations of a ray tracing processor. For instance, a process can include obtaining one or more nodes of an acceleration data structure. Each node of the one or more nodes includes the same number of bytes. The node(s) can be stored in a cache associated with a ray tracing processor. Each of the stored node(s) are cache line-aligned with the cache associated with the ray tracing processor. A first stored node of the stored node(s) can be provided to the ray tracing processor and processed by the ray tracing processor during a first clock cycle of the ray tracing processor. A second stored node of the stored node(s) can be provided to the ray tracing processor and processed by the ray tracing processor during a second clock cycle of the ray tracing processor.

Ray tracing processor

Methods and apparatus to perform matrix multiplication in a streaming processor

The present disclosure relates to methods and apparatus for graphics processing. The apparatus can obtain at least one input image including a plurality of pixels. Additionally, the apparatus can determine shading information for each of the plurality of pixels in the at least one input image. The apparatus can also determine a shading map based on the determined shading information for each of the plurality of pixels in the at least one input image. In some aspects, the apparatus can generate at least one output image based on the at least one input image and the determined shading map. The apparatus can also enhance a quality of the at least one output image. In some aspects, the quality of the at least one output image can be enhanced based on machine learning. Further, the apparatus can generate the at least one input image including the plurality of pixels.

Methods and apparatus for machine learning rendering

Techniques are described to perform a shuffle operation. Rather than using an all-lane to all-lane cross bar, a shuffler circuit having a smaller cross bar is described. The shuffler circuit performs the shuffle operation piecewise by reordering data received from processing lanes and outputting the reordered data.

Shuffler circuit for lane shuffle in SIMD architecture

Techniques are described for reordering commands to improve the speed at which at least one command stream may execute. Prior to distributing commands in the at least one command stream to multiple pipelines, a multimedia processor analyzes any inter-pipeline dependencies and determines the current execution state of the pipelines. The processor may, based on this information, reorder the at least one command stream by prioritizing commands that lack any current dependencies and therefore may be executed immediately by the appropriate pipeline. Such out of order execution of commands in the at least one command stream may increase the throughput of the multimedia processor by increasing the rate at which the command stream is executed.

Out-of-order command execution with sliding windows to maintain completion statuses

In an example, a method of transferring data may include synchronizing work-items corresponding to a first subgroup and work-items corresponding to a second subgroup with a barrier. The method may include performing an inter-subgroup data transfer between the first subgroup and the second subgroup.

Inter-subgroup data sharing

A graphics processing unit (GPU) may dispatch a first set of commands for execution on one or more processing units of the GPU. The GPU may receive notification from a host device indicating that a second set of commands are ready to execute on the GPU. In response, the GPU may issue a first preemption command at a first preemption granularity to the one or more processing units. In response to the GPU failing to preempt execution of the first set of commands within an elapsed time period after issuing the first preemption command, the GPU may issue a second preemption command at a second preemption granularity to the one or more processing units, where the second preemption granularity is finer-grained than the first preemption granularity.

Adaptive context switching

A SIMD processor may be configured to determine one or more active threads from a plurality of threads, select one active thread from the one or more active threads, and perform a divergent operation on the selected active thread. The divergent operation may be a serial operation.

Techniques for serialized execution in a SIMD processing system

This disclosure describes techniques for supporting inter-task communication in a parallel computing system. The techniques for supporting inter-task communication may use hardware-based atomic operations to maintain the state of a pipe. A pipe may refer to a First-In, First-Out (FIFO)-organized buffer that allows various tasks to interact with the buffer as data producers or data consumers. Various pipe implementations may use multiple state parameters to define the state of a pipe. The hardware-based atomic operations described in this disclosure may modify multiple pipe state parameters in an atomic fashion. Modifying multiple pipe state parameters in an atomic fashion may avoid race conditions that would otherwise occur when multiple producers and/or multiple consumers attempt to modify the state of a pipe at the same time. In this way, pipe-based inter-task communication may be supported in a parallel computing system.

Hardware-based atomic operations for supporting inter-task communication

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San Diego, CA, United States of America

Alexei Vladimirovich Bourd