Apple Inc.

Alexei Ouzilevaski

Mushtaq A Sarwar

Chien-Hsin Lin

Mike Lai

Methods and apparatuses for concatenating codewords of variable lengths using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to pack bit streams of variable lengths including: receiving a first bit segment from a first vector register; receiving a second bit segment from a second vector register; determining whether or not the sum of the bit length of the first bit segment and the bit length of the second bit segment is larger than a required length; generating a third bit segment from the first and second bit segments; and outputting the third bit segment in a third vector register; where the above operations are performed in response to the microprocessor receiving a first single instruction. The third bit segment is generated from concatenating the first bit segment and a beginning portion of the second bit segment such that the bit length of the third bit segment is equal to the required length when the sum is larger than the required length; and the third bit segment is generated from concatenating the first and second bit segments when the sum is not larger than the required length.

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Cupertino, CA, United States of America

Alexei Ouzilevaski