Power Integrations, Inc.

Alexei Ankoudinov

Sorin Stefan Georgescu

Vijay Parthasarathy

Kamal Raj Varadarajan

Jiankang Bu

Kelly Marcum

Kelly E Marcum

A superjunction device comprising a drain contact, a substrate layer above the drain contact, an epitaxial layer above the substrate layer, a P+ layer above the epitaxial layer formed by P-type implantation to a bottom of the superjunction device, a trench with a sloped angle formed by use of a hard mask layer. The trench is filled with an insulating material. A first vertical column is formed adjacent to the trench. A second vertical column is formed adjacent to the first vertical column. A source contact is coupled to the first vertical column and the second vertical column. A P-body region is coupled to the source contact. A gate oxide is formed above the source contact and the epitaxial layer, and a gate formed above the gate oxide.

Process and structure for a superjunction device

A vertical power transistor device includes a semiconductor layer of a first conductivity type, with a plurality of dielectric regions disposed in the semiconductor layer. The dielectric regions extend in a vertical direction from a top surface of the semiconductor layer downward. Each dielectric region has a rounded-square cross-section in a horizontal plane perpendicular to the vertical direction. Adjacent ones of the dielectric regions are laterally separated by a narrow region of the semiconductor layer. Each dielectric region has a cylindrical field plate member centrally disposed therein. The cylindrical field plate member extends in the vertical direction from the top surface downward to near a bottom of the dielectric region. The dielectric region laterally separates the cylindrical field plate member from the narrow region. A source region is disposed at the top surface, and a drain region is disposed at the bottom, of the semiconductor layer.

Vertical transistor device structure with cylindrically-shaped field plates

A semiconductor device including a dummy pillar and a plurality of racetrack pillars. The dummy pillar of semiconductor material extends in a first lateral direction. The plurality of racetrack pillars, including the semiconducting material, surrounds the dummy pillar. Each of the plurality of racetrack pillars has a first linear section, which extends in the first lateral direction, and a first rounded section to form a racetrack shape. The plurality of racetrack pillars includes a first racetrack pillar and a second racetrack pillar. The first racetrack pillar is disposed proximate to the dummy pillar and the second racetrack pillar surrounds the first racetrack pillar. The first racetrack pillar is disposed between the dummy pillar and the second racetrack pillar. The semiconductor device includes a plurality of spacing regions including a first spacing region that surrounds the dummy pillar and is disposed between the first racetrack pillar and the dummy pillar.

Growing community of inventors

San Jose, CA, United States of America

Alexei Ankoudinov