Teledyne Scientific and Imaging, LLC

Alexandros Papavasiliou

Jeffrey DeNatale

Philip Stupar

Robert L Borwick, Iii

Robert Mihailovich

Yu-Hua Kao Lin

William E Tennant

Graham J Martin

John Mansell

Adam Young

Jeff DeNatale

Alan Roll

A method of forming void-free, high aspect ratio through-substrate vias by 'bottom-up' electroplating. In one embodiment, the method requires providing a substrate, forming a dielectric layer on the substrate's bottom side, providing at least one perforation through the dielectric layer, forming a via hole through the substrate from its top side to the dielectric layer and over the perforations, forming an isolation layer on the sidewalls of the via hole, forming a metal seed layer on the bottom side of the dielectric layer, electroplating the seed layer such that all of the perforations are plugged, and electroplating up the via hole from the plugs to fill the via hole.

Through-substrate vias formed by bottom-up electroplating

An arrangement for making electrical contact to a vertical capacitor having top and bottom metal layers separated by a dielectric, and at least one trench. Recesses are formed in an oxide layer over the capacitor to provide access to the top and bottom metal layers. The recesses include contacting portions preferably positioned such that there is no overlap between them and any of the trenches. Metal in the recesses, preferably copper, forms electrical contacts to the vertical capacitor's metal layers and enables reliable bonding to copper metallization on other layers such as an ROIC layer. 'Dummy' capacitors may be tiled on portions of the IC where there are no vertical capacitors, preferably with the top surfaces of their top metal at a height approximately equal to that of the top surface of the vertical capacitor's top metal, thereby enabling the IC to be planarized with a uniform planarization thickness.

Vertical capacitor contact arrangement

A microelectromechanical shutter system includes an actuator beam formed in a substrate, at least one actuator electrode spaced apart and electrically isolated from the actuator beam, the at least one actuator electrode angling away from a base of the actuator beam to actuate the actuator beam using a zipper action, and a fiber-optic channel in the substrate to receive a fiber-optic cable. A shutter mirror is included on a distal end of the actuator beam, with the shutter mirror in substantial alignment with a centerline of the fiber-optic channel. Upon application of a voltage between the actuator beam and the at least one actuator electrode, an electrostatic force is created between them to move the shutter mirror across the end of the fiber-optic channel.

Microelectromechanical optical shutter system

An apparatus includes a chip-scale atomic clock (CSAC) alkali vapor cell seated on a silicon substrate that is suspended in a package by a metalized Parylene strap having Parylene anchors embedded in a silicon frame, the Parylene strap comprising an extended rigidizing structure, and a plurality of electrical pins extending into an interior of the package, the plurality of electrical pins in electrical communication with the CSAC cell through the metalized Parylene strap, where the CSAC cell is mechanically connected to the package and thermally insulated from the package.

Micro-scale system to provide thermal isolation and electrical communication between substrates

Microfabricated inductors with through-wafer vias and including a first wafer and a second wafer, each wafer having a plurality of metal fillings therein, and a plurality of metal conductors connecting the plurality of metal fillings together to form a spiral. A method for producing an inductor including steps of forming a first plurality of vias in a first substrate, filling the first plurality of vias in the first substrate with a first plurality of metal fillings, forming a first plurality of metal conductors, connecting pairs of the first plurality of metal fillings together using the first plurality of metal conductors to form a spiral, performing the foregoing steps similarly on a second substrate formed with a second plurality of vias filled with a second plurality of metal fillings, and bonding the first substrate with the second substrate.

Microfabricated inductors with through-wafer vias

An imaging array comprises a photodetector layer, a readout IC (ROIC) layer, and a charge storage capacitor layer which is distinct from the photodetector and ROIC layers; the layers are electrically interconnected to form the array. The capacitors within the charge storage capacitor layer are preferably micromachined; the charge storage capacitor layer can be an interposer layer or an outer layer.

Imaging array device structure with separate charge storage capacitor layer

A microscale apparatus includes a microscale rigidized Parylene strap having a reinforcement structure extending from a first side of the strap, a first silicon substrate suspended by the microscale rigidized Parylene strap, the microscale rigidized Parylene strap conformally coupled to the first substrate, and a second substrate conformally coupled to the microscale rigidized Parylene strap to suspend the first silicon substrate through the microscale rigidized Parylene strap.

An through-substrate via fabrication method requires forming a through-substrate via hole in a semiconductor substrate, depositing an electrically insulating, continuous and substantially conformal isolation material onto the substrate and interior walls of the via using ALD, depositing a conductive material into the via and over the isolation material using ALD such that it is electrically continuous across the length of the via hole, and depositing a polymer material over the conductive material such that any continuous top-to-bottom openings present in the via holes are filled by the polymer material. The basic fabrication method may be extended to provide vias with multiple conductive layers, such as coaxial and triaxial vias.

Through-substrate vias with polymer fill and method of fabricating same

A fabrication method which forms vertical capacitors in a substrate. The method is preferably an all-dry process, comprising forming a through-substrate via hole in the substrate, depositing a first conductive material layer into the via hole using atomic layer deposition (ALD) such that it is electrically continuous across the length of the via hole, depositing an electrically insulating, continuous and substantially conformal isolation material layer over the first conductive layer using ALD, and depositing a second conductive material layer over the isolation material layer using ALD such that it is electrically continuous across the length of the via hole. The layers are arranged such that they form a vertical capacitor. The present method may be successfully practiced at temperatures of less than 200&#xb0; C., thereby avoiding damage to circuitry residing on the substrate that might otherwise occur.

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Thousand Oaks, CA, United States of America

Alexandros Papavasiliou