Hrl Laboratories, LLC

Toyota Motor Engineering & Manufacturing North America, Inc.

Infineon Technologies Ag

Gm Global Technolgoy Operations, Inc.

The Boeing Company

Emag Technologies, Inc.

Intel Corporation

University of Michigan

Georgia Tech Research Corporation

Alexandros Margomenos

Miroslav Micovic

Keisuke Shinohara

Florian G Herrault

Andrea Corrion

David F Brown

Ara K Kurdoghlian

Melanie Sachiko Yajima

Hasan Sharifi

Linda P B Katehi

Eric M Prophet

Amin Rida

Igal Bilik

Paul Donald Schmalenberg

Serdar Hakki Yonak

Rongming Chu

Sang Won Yoon

Shawn D Burnham

Koji Shiozaki

Colleen M Butler

Ofir Degani

Ashoke Ravi

Elan Banin

Igal Kushnir

Dean C Regan

Benjamin Jann

Kazem F Sabet

Satwik Patnaik

Katherine J Herrick

Hsuanyu Pan

Manos Tentzeris

Hector L Bracamontes

Li Yang

Ruihua Ding

Yuxing Tang

Serdar Hakki Yönak

James P Becker

Ivan Alvarado-Rodriguez

Pan Hsuanyu

Ross L Bowen

Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.

Digital radio head control

An active quadrature generation circuit configured to provide an in-phase output signal and a quadrature output signal based on an input signal and a method of fabricating the active quadrature generation circuit on an integrated circuit are described. The circuit includes an input node to receive the input signal and a first transistor including a collector connected to a power supply pin. The circuit also includes a second transistor including a base connected to the power supply pin, the second transistor differing in size from the first transistor by a factor of K, wherein the in-phase output signal and the quadrature output signal are generated based on an inherent phase difference of 90 degrees between a current at a collector of the first transistor and a current at a base of the second transistor.

Active quadrature circuits for high frequency applications

A transmit/receive module includes a control circuit including multiple pairs of I/O terminals, each pair including a TX output terminal and an RX input terminal, a plurality of transmit/receive circuits connected to the control circuit, each of the transmit/receive circuits including a TX input terminal connected to the TX output terminal of one of the pairs of I/O terminals, an RX output terminal connected to the RX input terminal from the one of the pairs of I/O terminals, and a power amplifier connected to the TX input terminal. DC biasing terminals of each power amplifier of the transmit/receive circuits are independently connected to and controllable by the control circuit.

Transmitter/receiver module for millimeter wave 5G MIMO communication systems

Methods using chemical vapor deposition (CVD) of diamond deposited on a sacrificial material provide CVD diamond microchannel structures and 3-D interconnection structures of CVD diamond microfluidic channels. The sacrificial material is patterned to define locations and dimensions of the microchannels. The patterned sacrificial material is selectively removed from underneath the chemical vapor deposited (CVD) diamond to form the CVD diamond microchannels. The CVD diamond microchannels are integrated with electronic structures to provide an integral microfluidic cooling system to electronic devices.

Fabrication of microfluidic channels in diamond

A transmit/receive module includes an integrated control circuit. The integrated control circuit includes an RFIC input terminal, multiple pairs of I/O terminals, a power splitter/combiner having an input connected to the RFIC input terminal, a plurality of phase shifters connected between outputs of the power splitter/combiner and the I/O terminals, and a power sensor connected to each one of the I/O terminals. The integrated control circuit further includes a plurality of transmit/receive integrated circuits that each include a TX input terminal, an RX output terminal, an antenna interface terminal, a power amplifier connected, a low noise, and a switch connected between the power amplifier, the low noise amplifier and the antenna interface terminal. Gate and drain terminals of a final stage of each power amplifier of the transmit/receive integrated circuits are independently connected to and controllable by the integrated control circuit.

A method of mounting one or more semiconductor or microelectronic chips, which includes providing a carrier; temporarily adhering the one or more semiconductor or microelectronic chips to the carrier with active faces of the one or more chips facing towards the carrier; providing a package body with at least one chip-receiving opening therein and with at least one contact opening therein; temporarily adhering the package body to the carrier with the at least one opening in the package body accommodating at least a portion of the one or more chips; covering backsides of the one or more chips and filling empty spaces between the one or more chips and walls of the at least one opening in the package body with a metallic material; filling the at least one contact opening with the aforementioned metallic material; wirebonding contacts on the active faces of the one or more chips with contact surfaces in electrical communication with the metallic material in the at least one contact opening; and releasing package body with the one or more chips embedded in the metallic material from the carrier.

Surface mount package for semiconductor devices with embedded heat spreaders

A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist.

Stepped field plate wide bandgap field-effect transistor and method

A transmit/receive module includes an integrated control circuit that is configured to operate in transmit and receive modes. In the transmit mode, the integrated control circuit converts a digital input signal into a plurality of phase shifted RF transmit signals. In the receive mode, the integrated control converts an RF receive signal into a digital output signal. The transmit/receive module further includes a plurality of transmit/receive integrated circuits connected. Each of the transmit/receive integrated circuits amplify one of the RF transmit signals using a power amplifier during the transmit mode, and amplify one of the RF receive signals using a low noise amplifier during the receive mode. The integrated control circuit biases the power amplifier and calibrates a power level the power amplifier in the transmit mode. The integrated control circuit protects the integrated control circuit from damage by controlling the low noise amplifier during the receive mode.

An interconnect for electrically coupling pads formed on adjacent chips or on packaging material adjacent the chips, with an electrically conductive heat sink being disposed between the pads, the interconnect comprising a metallic membrane layer disposed between two adjacent pads and disposed or bridging over the electrically conductive heat sink so as to avoid making electrical contact with the electrically conductive heat sink. An electroplated metallic layer is disposed on the metallic membrane layer. Fabrication of interconnect permits multiple interconnects to be formed in parallel using fabrication techniques compatible with wafer level fabrication of the interconnects. The interconnects preferably follow a smooth curve to electrically connect adjacent pads and following that smooth curve they bridge over the intervening electrically conductive heat sink material in a predictable fashion.

Wafer-level die to package and die to die interconnects suspended over integrated heat sinks

A method of mounting a plurality of semiconductor or microelectronic chips or dies, the method including providing a carrier, temporarily adhering the plurality of semiconductor or microelectronic chips or dies to the carrier with active faces of the chips or dies facing towards the carrier, covering backsides of the chips and filling empty spaces between the chips or dies with a metallic material to thereby define an assembly of the chips or dies and the metallic material, and releasing the assembly from the carrier, wherein each chip or die comprises at least one bonding ring higher than a height of the active face of the respective chip or die or any connections on the active face of the respective chip or die.

Simultaneous controlled depth hot embossing and active side protection during packaging and assembly of wide bandgap devices

A single-to-differential converter and a method of fabricating the single-to-differential converter on an integrated circuit are described. The single-to-differential converter provides a pair of differential outputs based on a single-ended input and includes an input node to receive the single-ended input, and a first transistor connected to a power supply pin. A second transistor is connected to the power supply pin. The first transistor and the second transistor are biased under a same amount of direct current (DC) and the pair of differential outputs are generated at respective collectors of the first transistor and the second transistor.

Internally matched active single-to-differential RF converter

A method of forming an E-plane probe includes forming a plurality of monolithically integrated circuits (MICs) on a wafer, each MIC including a monolithic microwave integrated circuit (MMIC), and an E-plane probe coupled to the MMIC, mounting the wafer on an ultra-violet (UV) tape, cutting the wafer with a laser at a first power and a first linear cutting speed along vertical streets and then along horizontal streets to form separate substrates, cutting with the laser at a second power and a second linear cutting speed a rectangle or a portion of a rectangle from the separate substrates to form narrow substrate extensions on the substrates, and repeating this step for each rectangle or portion of a rectangle to be cut to form substrate extensions, and curing the UV tape, wherein the E-plane probes are on the narrow substrate extensions.

E-plane probe with stepped surface profile for high-frequency

A method for wafer level packaging includes forming one or more die, forming a plated metal ring (PMR) on each die, forming a cover wafer (CW), the CW having one or more plated seal rings, forming a body wafer (BW), the BW having cavities and a metal layer on a first side of the BW, aligning a respective die to the CW so that a PMR on the respective die is aligned to a respective plated seal ring (PSR) on the CW, bonding the PMR on the respective die to the respective PSR, aligning the BW to the CW so that a respective cavity of the BW surrounds each respective die bonded to the CW and so that the metal layer on the BW is aligned with at least one PSR on the CW, and bonding the metal layer on the first side of the BW to the PSR on the CW. Each PMR has a first height and each PSR has a second height.

Direct IC-to-package wafer level packaging with integrated thermal heat spreaders

Apparatus and methods are provided for heat removal and spreading from a field effect transistor (FET) including a substrate, a first source, a first gate, and a drain on the substrate, and a poly-diamond dielectric thermally coupled to the first gate wherein the poly-diamond dielectric facilitates heat removal from a top of the FET.

Near junction cooling for GaN devices

Growing community of inventors

Pasadena, CA, United States of America

Alexandros Margomenos