Intel Corporation

Hicamp Systems, Inc.

Other

Alexandre Y Solomatnikov

David R Cheriton

Amin Firoozshahian

Chandan Egbert

Andreas Kleen

Mahesh Srinivasa Maddury

Omid Azizi

Mahesh Madhav

David Hansen

Ashok Raj

Stephen R Van Doren

John Peter Stevenson

Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.

Hardware-assisted paging mechanisms

Various systems and methods for computer memory management are described herein. A system includes a memory controller to: monitor utilization of a memory device, the memory device used with a memory compression technique; determine that the utilization of the memory device violates a threshold; and initiate a system interrupt to provoke a response, responsive to the utilization of the memory device violating the threshold.

Memory pressure notifier

Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain. Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element. A local state associated with a selected iterator register is generated by performing one or more register operations relating to the selected iterator register and involving pointers in the pointer fields of the selected iterator register. A pointer-linked data structure is updated in the memory system according to the local state.

Iterator register for structured memory

A memory controller is used to receive a first request for a portion of a physical memory and metadata associated with the portion of the physical memory. The first request for the portion of the physical memory is translated to correspond to an indirect data structure. The indirect data structure comprises a reference to a data line, and a metadata associated with the data line. The data line is formed within the physical memory.

Hardware-supported per-process metadata tags

Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory.

Hierarchical immutable content-addressable memory coprocessor

Structured memory coprocessor

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Palo Alto, CA, United States of America

Alexandre Y Solomatnikov