Commissariat a L'energie Atomique

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics S.a.

Alexandre Valentian

Laurent Grenouillet

Elisa Vianello

Olivier Thomas

Marc Belleville

Olivier Bichler

Sylvain Engels

Philippe Flatresse

Sylvain Majcherczak

François Rummens

Julien Le Coz

Dimitri Soussan

Thomas Mesquida

An artificial neuron for a neuromorphic chip comprises a synapse with resistive memory representative of a synaptic weight. The artificial neuron comprises a read circuit, an integration circuit and a logic circuit interposed between the read circuit and the integration circuit. The read circuit is configured to impose on the synapse a read voltage independent of the membrane voltage and to provide an analogue value representative of the synaptic weight. The logic circuit is configured to generate from the analogue value a pulse having a duration. The integration circuit comprises an accumulator of synaptic weights at the terminals of which a membrane voltage is established and a comparator configured to emit a postsynaptic pulse if a threshold is exceeded by the membrane voltage. Moreover, it comprises a source of current controlled by the pulse to inject a current into the accumulator of synaptic weights during this duration.

Artificial neuron for neuromorphic chip with resistive synapses

An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.

Integrated circuit comprising at least one digital output port having an adjustable impedance, and corresponding adjustment method

A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage.

Transistor substrate dynamic biasing circuit

The invention relates to electronic integrated circuits capable of operating either in active mode or in standby mode and of having, in standby mode, a very low current consumption. According to the invention, the leakage current of a power transistor inserted in series between a supply terminal and an active circuit is controlled by a gate reverse overbias in the following manner: a voltage step-up charge pump generates a gate bias voltage from pulses delivered by an oscillator having its frequency controlled by a current. The control current Ic is the leakage current of a transistor having technological characteristics similar to those of the power transistor. The system optimizes the current consumption in standby mode, the frequency of the oscillator being reduced when the gate is biased so as to minimize the leakage current. The invention is applicable to circuits powered by a battery or a cell (mobile telephones, cameras, portable computers, etc.).

Integrated circuit with a power transistor gate bias controlled by the leakage current

The invention concerns a process and a circuit designed to improve the life duration of electronic field-effect integrated circuit transistors and in particular those with a thin film gate dielectric. According to the invention, an aging measurement tis supplied by measuring the charge or discharge time at a reference voltage Vof the gate of a field effect transistor T, previously pre-charged to a predefined test voltage V, and brought to high impedance. Depending on the aging measurement obtained, the operational voltage measurement conditions of the transistor can be maintained or modified to reduce the stress applied to the dielectric.

Process and circuit for improving the life duration of field-effect transistors

The invention relates to electronic integrated circuits capable of operating either in active mode or in standby mode and to have, in standby mode, a very low current consumption. According to the invention, the leakage current of a power transistor inserted in series between a supply terminal and an active circuit is controlled by a gate reverse overbias in the following manner: a first reference transistor, and a second reference transistor identical to the first, are biased with the same gate reverse overbias voltage as the power transistor, the first transistor having its source linked to the supply terminal, and the second reference transistor having its source linked to its drain. The leakage currents in these two transistors are compared, and it is considered that the optimal bias of the gate is obtained when the leakage currents are equal. Applications to circuits supplied by a battery or a cell (portable telephones, cameras, portable computers, etc.).

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Saint Egreve, France

Alexandre Valentian