Sifive, Inc.

Alexandre Solomatnikov

David Kravitz

Bradley Gene Burgess

Krste Asanovic

Josh Smith

Drew Barbier

David Parry

Systems and methods are disclosed for transferring data between a memory system and a vector register file. For example, a system may include a vector pipeline including a vector physical register file; a load store unit; one or more pipeline stages configured to decode a vector memory instruction to obtain a macro-operation and dispatch the macro-operation to both the load store unit and the vector pipeline, and a baler circuitry, including a buffer with entries. The vector pipeline is configured to crack the macro-operation into multiple micro-operations. The baler circuitry is configured to implement the multiple micro-operations to transfer data between one or more selected entries of the buffer and respective registers of the vector physical register file. The load store unit is configured to implement the macro-operation to transfer data between one or more addresses in a memory system and the one or more selected entries of the buffer.

Vector load store operations in a vector pipeline using a single operation in a load store unit

Systems and methods are disclosed for a configurable interconnect address remapper with event detection. For example, an integrated circuit can include a processor core configured to execute instructions. The processor core includes region registers defined by a From Address range and a To Address, a register storing a number of regions defined in the integrated circuit, interrupt enable registers associated with each pair of region registers, and event flags associated with each pair of region registers; an interconnection system handling transactions from the processor core; an interconnect address remapper translating an address associated with a transaction using the one or more pair of region registers; and an interrupt controller receiving an interrupt signal from the interconnect address remapper when the interrupt enable registers are enabled and at least one raised event flags when at least one of the one or more pair of region registers matches the transaction address.

Technologies for interconnect address remapper with event recognition and register management

Apparatus and methods which bundle micro-operations with respect to a vector instruction, dynamically allocate register blocks for a vector instruction, and track the registers using valid bits. A method includes decoding, by a decoder, a vector instruction having a length multiplier of at least two into a number of micro-operations less than the length multiplier, allocating, by an issue queue, an issue queue entry to each of the number of micro-operations and executing, by the issue queue with execution units, each of the number of micro-operations a number of times from the issue queue entry to collectively match the length multiplier.

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San Carlos, CA, United States of America

Alexandre Solomatnikov