Texas Instruments Corporation

Robert Boschgmbh

Nxp Usa, Inc.

Alexandre Pierre Palus

Karl Friedrich Greb

Kevin Patrick Lavery

Yanyang Xiao

Paul William Krause

Manfred P Thanner

Harald Tschentscher

Carsten Gebauer

Anthony M Reipold

Peter Sautter

Stephan G Mueller

Berthold Fehrenbacher

Roy M Haley

Charles Ming-Fong Tsai

Venkata Kishore Gadde

Hoi-Man Low

In at least one embodiment of the disclosure, a method includes detecting an error in a local memory shared by redundant computing modules executing in delayed lockstep. The method includes pausing execution in the redundant computing modules and handling the error of the local memory. The method includes resuming execution in delayed lockstep of the redundant computing modules in response to the handling of the error.

Multi-channel network-on-a-chip

An embodiment of the invention provides a method for changing a multi-processor system from a performance mode to a safety mode while the system continues to run software. When an external event or exception occurs, context is switched from the performance mode to the safety mode. After context is switched, at least one pair of CPUs is synchronized to operate in the safety mode. In addition, a multi-processor system may be switched form the safety mode to the performance mode while the software continues to operate.

Locking/unlocking CPUs to operate in safety mode or performance mode without rebooting

An electronic circuit includes a microcontroller processor (), a peripheral () coupled with the processor, an endian circuit () coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit () to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Endian configuration memory and ECC protecting processor endianess mode circuit

Encode and multiplex, register, and decode and error correction circuitry

In order to detect a faulty error correcting unit () in an embedded system, wherein the error correcting unit () receives output data from a data source () and determines, whether the received data are incorrect, and wherein if the received data are incorrect, the error correcting unit () is expected to correct at least one error within the received data, output the corrected data and manipulate an error vector (), a method and a system (Ia) are suggested that enable to compare the output data of the error correcting unit () with at least one reference data, wherein the at least one reference data originate at least indirectly from the data source (). Both, the error vector () and the result of the comparison are input to a plausibility test in order to decide, whether the error correcting unit () is faulty. According to the result of the plausibility test, a failure vector () is manipulated in order to indicate whether a failure in the error correcting unit () is detected.

Method and system for detecting a failure in an error correcting unit

Growing community of inventors

Austin, TX, United States of America

Alexandre Pierre Palus