Intel Corporation

Alexandre J Farcy

Martin Guy Dixon

Mark C Davis

Gilbert M Wolrich

Bret L Toll

Sean Mirkes

Vinodh Gopal

Wajdi K Feghali

James D Guilford

Erdinc Ozturk

Maxim Loktyukhin

Avinash Sodani

Matthew C Merten

Stephan Jourdan

Per H Hammarlund

Ilhyun Kim

James Hadley

Morris Marden

Robert L Hinton

Konrad K Lai

Ravi Rajwar

Robert S Chappell

Rajesh S Parthasarathy

John Alan Miller

Vijaykumar Balaram Kadgi

Prakash Math

Iredamola Dammy Olopade

Choon Wei Khor

Lihu Rappoport

Srikanth T Srinivasan

Paul Caprioli

Douglas M Carmean

Sebastien Hily

Tong Li

Chen Koren

Justin M Deinlein

Yury N Ilin

Pierre Michaud

Erdine Ozturk

Vindoh Gopal

Maxim Loktyukin

James D Gulilford

Waidi K Feghali

A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Rotate instructions that complete execution either without writing or reading flags

A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

Multiplication instruction for which execution completes without writing a carry flag

An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution

Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution

A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.

Apparatus including a stall counter to bias processing element selection, and masks to allocate reservation unit entries to one or more processing elements

An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.

Enhanced loop streaming detector to drive logic optimization

This disclosure includes tracking of in-use states of cache lines to improve throughput of pipelines and thus increase performance of processors. Access data for a number of sets of instructions stored in an instruction cache may be tracked using an in-use array in a first array until the data for one or more of those sets reach a threshold condition. A second array may then be used as the in-use array to track the sets of instructions after a micro-operation is inserted into the pipeline. When the micro-operation retires from the pipeline, the first array may be cleared. The process may repeat after the second array reaches the threshold condition. During the tracking, an in-use state for an instruction line may be detected by inspecting a corresponding bit in each of the arrays. Additional arrays may also be used to track the in-use state.

Multi-level tracking of in-use state of cache lines

Embodiments of an invention for a load instruction for code conversion are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction having a source operand to indicate a source location and a destination operand to indicate a destination location. The execution unit is to execute the instruction. Execution of the instruction includes checking the access permissions of the source location and loading content from the source location into the destination location if the access permissions of the source location indicate that the content is executable.

System and method for a load instruction with code conversion having access permissions to indicate failure of load content from registers

Rotate instructions that complete execution without reading carry flag

This disclosure provides techniques and apparatuses to enable early, run-ahead handling of IC and ITLB misses by decoupling the ITLB and IC tag lookups from the IC data (instruction bytes) accesses, and making ITLB and IC tag lookups run ahead of the IC data accesses. This allows overlapping the ITLB and IC miss stall cycles with older instruction byte reads or older IC misses, resulting in fewer stalls than previous implementations and improved performance

Hiding instruction cache miss latency by running tag lookups ahead of the instruction accesses

Growing community of inventors

Hillsboro, OR, United States of America

Alexandre J Farcy