International Business Machines Corporation

Globalfoundries Inc.

Barcelona Supercomputing Center-centro Nacional De Supercomputacion

Barcelona Supercomputing Center

Alexandre E Eichenberger

Peng Wu

Kathryn Mary O'Brien

Michael K Gschwind

Kai-Ting Amy Wang

John Kevin O'Brien

John A Gunnels

Zehra Noman Sura

John K P O'Brien

Alan G Gara

Brian King Flachs

John Kevin Patrick O'Brien

Charles Ray Johns

Mark Richard Nutter

Martin Ohmacht

Tong Chen

Xiaotong Zhuang

Peng Zhao

Bruce Martin Fleischer

Carlo Bertolli

Valentina Salapura

Tao Zhang

Marc Gonzalez Tallada

Nicolas T Vasilache

George L Chiu

Dong Chen

Paul William Coteus

Michael A Blocksome

Joseph D Ratterman

Philip Heidelberger

Adam James Muff

Todd Edward Takken

Vijayalakshmi Srinivasan

Thomas M Gooding

Robert William Wisniewski

Mark Edwin Giampapa

Burkhard Steinmacher-Burow

Mark Gregory Megerian

Sameh W Asaad

Matthias Augustin Blumrich

Shawn Anthony Hall

Thomas Winters Fox

Chen-Yong Cher

Barry Marshall Trager

Charles David Wait

Sameer Kumar

John-David Wellman

James Anthony Marcella

Todd Alan Inglett

Krishnan Sugavanam

Gerard Vincent Kopcsay

Jeffrey John Parker

Robert Matthew Senger

Noel A Eisley

Lakshminarayanan Renganarayana

Rudolf Adriaan Haring

David L Satterfield

Douglas R Miller

Craig Brian Stunkel

Amith R Mamidala

Yutaka Sugawara

Kristan D Davis

Jose R Brunheroto

Michael B Mundy

Matthew Roger Ellavsky

Robert E Walkup

James Lee Van Oosten

Samuel J Miller

Arpith C Jacob

Gabor J Dozsa

Ruth Janine Poole

Peter Boyle

Brant L Knudson

Ralph E Bellofatto

Norman Christ

Kahn C Evans

William Maupin Stockdell

Alfred Thomas Watson, Iii

Eduard Ayguade

Xavier Martorell

Amy K Wang

Samuel F Antao

Brian E Smith

Brett Olsson

Sumedh Wasudeo Sathaye

Ulrich Weigand

Raul Esteban Silvera

Roch Georges Archambault

Erik Richter Altman

Fred Gehrung Gustavson

James Lawrence McInnes

Guansong Zhang

Ayal Zaks

Mark Peter Mendell

Ira Rosen

Dorit Nuzman

Yuan Zhao

Yangchun Luo

Amy Kai-Ting Wang

Amy (k T) Wang

A method includes a computer device receiving a branch instruction; the computer device managing two tables, where a first table relates to application blocks and a second table relates to available address slots; and the computer device calculating a target of the branch instruction using a branch-to-link register, the computer device optimizes re-wiring in a cache using the calculation and the managed two tables.

Optimizing branch re-wiring in a software instruction cache

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

Embodiments relate to program structure-based blocking. An aspect includes receiving source code corresponding to a computer program by a compiler of a computer system. Another aspect includes determining a prefetching section in the source code by a marking module of the compiler. Yet another aspect includes performing, by a blocking module of the compiler, blocking of instructions located in the prefetching section into instruction blocks, such that the instruction blocks of the prefetching section only contain instructions that are located in the prefetching section.

Program structure-based blocking

Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor. Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.

Parallel execution unit that extracts data parallelism at runtime

Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor, Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.

Mechanisms are provided for dynamic data driven alignment and data formatting in a floating point SIMD architecture. At least two operand inputs are input to a permute unit of a processor. Each operand input contains at least one floating point value upon which a permute operation is to be performed by the permute unit. A control vector input, having a plurality of floating point values that together constitute the control vector input, is input to the permute unit of the processor for controlling the permute operation of the permute unit. The permute unit performs a permute operation on the at least two operand inputs according to a permutation pattern specified by the plurality of floating point values that constitute the control vector input. Moreover, a result output of the permute operation is output from the permute unit to a result vector register of the processor.

All-to-all permutation of vector elements based on a permutation pattern encoded in mantissa and exponent bits in a floating-point SIMD architecture

Mechanisms for performing a matrix multiplication operation are provided. A vector load operation is performed to load a first vector operand of the matrix multiplication operation to a first target vector register. A pair-wise load and splat operation is performed to load a pair of scalar values of a second vector operand and replicate the pair of scalar values within a second target vector register. An operation is performed on elements of the first target vector register and elements of the second target vector register to generate a partial product of the matrix multiplication operation. The partial product is accumulated with other partial products and a resulting accumulated partial product is stored. This operation may be repeated for a second pair of scalar values of the second vector operand.

Matrix multiplication operations using pair-wise load and splat operations

Mechanisms, in a data processing system comprising a single instruction multiple data (SIMD) processor, for performing a data dependency check operation on vector element values of at least two input vector registers are provided. Two calls to a simd-check instruction are performed, one with input vector registers having a first order and one with the input vector registers having a different order. The simd-check instruction performs comparisons to determine if any data dependencies are present. Results of the two calls to the simd-check instruction are obtained and used to determine if any data dependencies are present in the at least two input vector registers. Based on the results, the SIMD processor may perform various operations.

SIMD compare instruction using permute logic for distributed register files

In one embodiment, a computer-implemented method includes tracking a size of a load-store queue (LSQ) during compile time of a program. The size of the LSQ is time-varying and indicates how many memory access instructions of the program are on the LSQ. The method further includes scheduling, by a computer processor, a plurality of memory access instructions of the program based on the size of the LSQ.

Schedulers with load-store queue awareness

The present disclosure relates generally to a dedicated memory structure (that is, hardware device) holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute.

Dedicated memory structure holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute

A computer-implemented method includes selecting a runtime for executing a program. The runtime includes a first combination of feature implementations, where each feature implementation implements a feature of an application programming interface (API). Execution of the program is monitored, and the execution uses the runtime. Monitor data is generated based on the monitoring. A second combination of feature implementations are selected, by a computer processor, where the selection is based at least in part on the monitor data. The runtime is modified by activating the second combination of feature implementations to replace the first combination of feature implementations.

Adaptive runtime for a multiprocessing API

Systems, methods and computer products for cross-thread scheduling. Exemplary embodiments include a cross thread scheduling method for compiling code, the method including scheduling a scheduling unit with a scheduler sub-operation in response to the scheduling unit being in a non-multithreaded part of the code and scheduling the scheduling unit with a cross-thread scheduler sub-operation in response to the scheduling unit being in a multithreaded part of the code.

Systems, methods and computer products for cross-thread scheduling

Growing community of inventors

Chappaqua, NY, United States of America

Alexandre E Eichenberger