Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Renault

Renault S.a.s.

Alexandre Carbon

Jean-Marc Philippe

Olivier Bichler

Renaud Sirdey

Marc Duranton

Nicolas Ventroux

Raphaël David

Laurent Le Garff

Robert Faure

Laurent Forgeot

Yves Lhuiller

Jean-Yves Stineau

Joël Cathebras

The electronic architecture carries out the management of the functions of a vehicle, the functions being implemented via a set of sensors and actuators, the architecture comprising at least: a central computer; a real-time communication network; a set of interface modules, each module: aggregating signals from at least one of the sensors and sending the signals to the central computer via the communication network; and/or distributing control signals to at least one of the actuators; the central computer driving the actuators according to the signals from the sensors, the control signals for the actuators being sent to the interface modules via the communication network.

Electronic architecture for onboard system

A circuit comprises a series of calculating blocks that can each implement a group of neurons; a transformation block that is linked to the calculating blocks by a communication means and that can be linked at the input of the circuit to an external data bus, the transformation block transforming the format of the input data and transmitting the data to said calculating blocks by means of K independent communication channels, an input data word being cut up into sub-words such that the sub-words are transmitted over multiple successive communication cycles, one sub-word being transmitted per communication cycle over a communication channel dedicated to the word such that the N channels can transmit K words in parallel.

Electronic circuit, particularly for the implementation of neural networks with multiple levels of precision

A neuron circuit is capable of producing a weighted sum of digitized input signals and applying an activation function to the weighted sum so as to produce a digitized activation signal as output. The circuit includes at least: one multiplier multiplying each input signal (xto x) with a weight value (wto w), one accumulator accumulating the results of the multiplier so as to produce the weighted sum, and one activation unit executing the activation function. The activation unit comprises at least one shift unit and at least one saturation unit capable of approximating a non-linear activation function. The result of the approximated activation function is obtained by one or more arithmetic shifts applied to the weighted sum.

Optimized neuron circuit, and architecture and method for executing neural networks

A compilation system for at least one instruction flow to be executed on a target circuit comprises a hardware acceleration circuit performing the functions of loading a set of at least one portion of said flow to a memory internal to the circuit and of decoding the set; the instructions resulting from the loading and from the decoding being transmitted to a programmable core operating in parallel to the hardware acceleration circuit, the programmable core producing the transcription of the decoded instructions into a machine code suitable for execution on the target circuit.

System for dynamic compilation of at least one instruction flow

Growing community of inventors

Bures sur Yvette, France

Alexandre Carbon