Cadence Design Systems, Inc.

Numerical Technologies, Inc.

Alexandre Arkhipov

Karun Sharma

Roland Ruehl

Giles V Powell

Shao-Po Wu

Jeffrey Markham

Seonghun Cho

Ilya Henry Grishashvili

Disclosed are techniques for implementing DRC clean multi-patterning process nodes with lateral fills. These techniques identify design rules governing multi-patterning and track patterns by accessing a rule deck to retrieve the design rules, identify a first shape and a second shape sandwiching a space and characteristics of the first and second shapes by examining design data of the electronic design, insert one or more lateral fill shapes in the space by implementing the one or more lateral fill shapes along one or more routing tracks of a legal track pattern while automatically complying with the design rules, and perform post-lateral fill or post-layout operations to improve the layout and to prepare the layout for manufacturing.

Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with lateral fills in electronic designs

Disclosed are techniques for implementing parallel fills for bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic processing. These techniques identify a canvas in a layout and design rules for track patterns and multiple-patterning, where the canvas is not yet associated with any base track patterns. A first shape having the first width is inserted along a first track in the canvas based on the design rules. A custom, legal track pattern is generated by arranging multiple tracks in an order and further by associating the first width with the first track in the custom, legal track pattern. The layout may then be further modified by guiding the insertion of one or more additional shapes with the custom, legal track pattern.

Methods, systems, and computer program product for a bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic techniques

Disclosed are techniques for implementing parallel fills for electronic designs These techniques identify a shape and one or more neighboring shapes of the shape by searching design data of a region of a layout of an electronic design, classify the shape and the one or more neighboring shapes by examining respective characteristics of and to categorize the shape and the one or more neighboring shapes into one or more classes, implement one or more parallel fill shapes for at least one shape of the shape and the one or more neighboring shapes by aggregating the one or more parallel fill shapes to the at least one shape based in part or in whole upon the one or more classes while automatically satisfying one or more design rules, and perform one or more post-layout operations on the layout including the one or more parallel fill shapes.

Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with parallel fills in electronic designs

Methods and systems for checking or verifying shapes in electronic designs are disclosed. The method identifies a dictionary (if pre-existing) or determining the dictionary by creating the dictionary and reduces dimensionality of design data by using a sliced line. Shapes are transformed into sliced line segments along the sliced line. Dictionary entries for shapes are associated with corresponding sliced line segments, and the design is checked or verified using the sliced line segments and the associated dictionary entries rather than using two-dimensional shapes or geometric data. Sliced line segments may be further partitioned or merged. Non-conforming shapes corresponding to no tracks of track patterns are identified and determined whether violations of design rules or requirements may be resolved by one or more other shapes using the corresponding sliced line segments.

Method, system, and computer program product for checking or verifying shapes in track patterns for electronic circuit designs

One embodiment of the invention provides a system that automatically resolves conflicts between phase shifters during creation of a phase shifting mask to be used in an optical lithography process for manufacturing an integrated circuit. Upon receiving a specification of a layout on the integrated circuit, the system identifies critical-dimension features within the layout. Next, the system places phase shifters comprised of phase shifting geometries on the phase shifting mask to precisely define the critical-dimension features. In doing so, the system identifies junctions within and/or between the critical-dimension features, and removes phase shifting geometries associated with the junctions to obviate coloring conflicts between phase shifters on the phase shifting mask. In one embodiment of the invention, the junctions include T-junctions and/or L-junctions.

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San Jose, CA, United States of America

Alexandre Arkhipov