Sun Microsystems, Inc.

Alexandra R Ohlson

John L Furlani

David T Berry

Richard T Inman

Apparatus, methods, systems and computer program products are disclosed that optimize the application of deferred image operations on a tiled source image. The invention dynamically creates a data structure (such as a directed acyclic graph (DAG)) representing the operations performed on various instances of one or more images to create a final image. The invention analyzes the data structure to determine which source image tiles are needed when the actual image data comprising the final image is required. Each of these tiles are then separately processed by all of the deferred operations to create the final image data. This approach reduces the number of times a tile is read into memory for processing and improves the performance of deferred image operations on a tiled source image.

Method, apparatus and computer program product for using deferred execution for a tiling pull model in a tiled image processing architecture

Apparatus, methods, and computer program products are disclosed for reducing the overhead associated with performing area-image operations on a tiled image. The invention detects when an area-image operation, that uses a source pixel contribution map, requires pixel values from one or more adjacent tiles. The invention also generates a list of boxes that represent pixel image information. These boxes are split with respect to the image edges and the tile edges within the image. The split boxes are used to direct memory buffer allocation for cobbled portions of the image and to leave the majority of the tile's pixel information to be operated on within memory buffer holding the tile. Thus, the invention provides a mechanism to assemble image data that crosses tile edges without copying major portions of the tile from one memory buffer to another. Additionally, each resulting box represents sufficient pixel values such that existing image processing techniques currently are applied to area-image operations can also be applied to tiled images. Thus, box can be processed by an MMX-like instruction or image hardware accelerator.

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Palo Alto, CA, United States of America

Alexandra R Ohlson