Infineon Technologies Austria Ag

Alexandra Ludsteck-Pechloff

Ralf Otremba

Alexander Heinrich

Daniel Pedone

Paul Frank

Frank Dieter Pfirsch

Frank Hille

Philip Christoph Brandt

Viktoryia Uhnevionak

A semiconductor package includes a power semi conductor chip comprising SiC, a leadframe part including Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint includes at least one intermetallic phase.

Semiconductor package and method for fabricating a semiconductor package

A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.

A power semiconductor transistor includes an electrically conductive contact structure including a plurality of contacts. A first one of the contacts is electrically connected to both a first load terminal and a first zone of a doped semiconductor structure. A second one of the contacts is electrically coupled to one of the first load terminal and a control electrode. The second contact laterally overlaps with both a second zone of the doped semiconductor structure, and a gap is formed between two adjacent field plates. The second zone of the doped semiconductor structure terminates in a section laterally overlapping with the gap.

High voltage termination structure of a power semiconductor device

Growing community of inventors

Unterhaching, Germany

Alexandra Ludsteck-Pechloff