Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Alexandra Bauche

Nian Niles Yang

Gautham Reddy

Jianmin Huang

Steven Theodore Sprouse

Niles Yang

Yichao Huang

Jian Feng Chen

Dana Lee

Chris Avila

William S Wu

Uday Chandrasekhar

Phil Reusswig

Nagdi Tafish

Michael Zhu

Improving performance of a read in a memory system. Various methods include: reading data from a word line in a memory block, where during the read, associated parameters are generated that include: a value indicative of a throughput time, and a value indicative of a bit error rate (BER); retrieving the value indicative of the throughput time and the value indicative of the BER; and performing a read improvement process if the value indicative of the throughput time is above a threshold value. The method also includes performing the read improvement process by: flagging the memory block if the value indicative of the BER is at or below and expected BER; and performing cleanup operations if the value indicative of the BER is higher than the expected BER.

Performance of a read in a memory system

An exemplary method to rank blocks of a non-volatile memory device includes: for each of a plurality of blocks of a memory device, determining a respective erase health metric (EHM) for each of the blocks by combining an erase difficulty metric and an age metric, including: calculating the erase difficulty metric for a respective block based on erase performance metrics obtained during erase phases of an erase operation performed on the respective block, and determining the age metric for the respective block based on a total number of erase operations performed on the respective block during its lifespan. After determining the respective EHM for each of the blocks, the method includes ranking blocks in accordance with the determined respective EHMs, and selecting a block of the plurality of blocks in accordance with the rankings, and writing data to the selected block.

Erase health metric to rank memory portions

A memory system or flash card may include a dynamic system-level process for the management of blocks in the different memory pools. There may be spare blocks available to the pools that are over provisioned to the pool which increases the efficiency of data compaction and helps reduce the average hot count for that pool and compensate for the grown defects. The block wear and grown defects in each memory pool may be tracked so that remaining spare blocks can be re-allocated.

Smart dynamic wear balancing between memory pools

The various implementations described herein include systems, methods and/or devices used to enable multi-phase erasure in a storage device. The method includes performing an erase operation on a portion of one or more non-volatile memory devices, by performing a sequence of erase phase operations until an erase operation stop condition is satisfied. Each erase phase operation includes: performing an erase phase on the portion of the non-volatile memory devices using an erase voltage, and determining an erase phase statistic for the erase phase. For each erase phase operation in the sequence of erase phase operations, other than a first erase phase operation, the erase voltage used when performing the erase phase operation is equal to the erase voltage used when performing a prior erase phase operation in the sequence of erase phase operations plus an erase voltage increment based on the erase phase statistic for the prior erase phase operation.

Adaptive multi-phase erase

A memory system or flash card may include memory maintenance scheduling that improves the endurance of memory. Certain parameters, such as temperature, are measured and used for scheduling maintenance. For example, memory maintenance may be performed or postponed depending on the ambient temperature of the card. The memory maintenance operations may be ranked or classified (e.g. in a memory maintenance queue based on priority) to correspond with threshold values of the parameters for a more efficient scheduling of memory maintenance. For example, at a low temperature threshold, only high priority maintenance operations are performed, while at a higher temperature threshold, any priority maintenance operation is performed.

Temperature based flash memory system maintenance

A memory system or flash memory device may include identify a bit error rate (BER) mapping for the memory. The BER mapping may be used for identifying erroneous bits, managing them, and using them for the system maintenance and system recovery. A complete BER map may be stored in main memory while a cached version of the BER map may be stored in random access memory (RAM). The cached version may identify only the top and bottom bits rather than the complete map. The cached BER map may be updated based on future reads and future programming may rely on the cached BER map for selecting blocks to program.

Bit error rate mapping in a memory system

Data stored in a nonvolatile memory is selectively sampled based on write-erase cycle counts of blocks. Blocks with the lowest write-erase cycle counts are sampled to determine an error rate which is compared with a limit. If the error rate exceeds the limit then the sample is expanded to include blocks with the next lowest write-erase cycle counts.

Selective sampling of data stored in nonvolatile memory

Non-volatile memory and methods of reading non-volatile memory are provided for managing and reducing read related disturb. Techniques are introduced to reduce read disturb using state-dependent read pass voltages for particular word lines during a read operation. Because of their proximity to a selected word line, adjacent word lines can be biased using state-dependent pass voltages while other unselected word lines are biased using a standard or second set of pass voltages. Generally, each state-dependent pass voltage applied to a word line adjacent to the selected word line is larger than the second set of pass voltages applied to other unselected word lines, although this is not required. Other word lines, may also be biased using state-dependent pass voltages. System-level techniques are provided with or independently of state-dependent pass voltages to further reduce and manage read disturb. Techniques may account for data validity and memory write and erase cycles.

Systems and methods for read disturb management in non-volatile memory

In a flash memory, erase blocks containing shorted or broken word lines may be used, at least in part, to store user data. Such blocks may use different parameters to those used by non-defective blocks, may be subject to different wear leveling, and may store data selected to reduce the number of access operations.

Defective block management

A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation.

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San Jose, CA, United States of America

Alexandra Bauche