Intel Corporation

Alexandr Titov

Stanislav Shwartsman

Zeev Sperber

Hong Wang

Sreenivas Subramoney

Joseph Nuzman

Lihu Rappoport

Robert S Chappell

Ronak Singhal

Adi Yoaz

Jayesh Gaur

Pavel I Kryukov

Pooja Roy

Dmitry Maslennikov

Pavel Matveyev

Valentin Burov

A processor including an execution unit, an instruction scheduler circuit to identify a first instruction of an instruction stream, identify a second instruction on which execution of the first instruction depends, and assign a first dispatch priority value to the first instruction and the second instruction, and a dispatch circuit to dispatch, based on the first dispatch priority value, the first instruction and the second instruction to an instruction execution circuit.

Criticality based port scheduling

An example system on a chip (SoC) includes a cache, a processor, and a predictor circuit. The cache may store data. The processor may be coupled to the cache and store a first data set at a first location in the cache and receive a first request from an application to write a second data set to the cache. The predictor circuit may be coupled to the processor and determine that a second location where the second data set is to be written to in the cache is nonconsecutive to the first location, where the processor is to perform a request-for-ownership (RFO) operation for the second data set and write the second data set to the cache.

Sequential data writes to increase invalid to modified protocol occurrences in a computing system

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Severodvinsk, Russia

Alexandr Titov