Intel Corporation

Alexander Uan-Zo-Li

James G Hermerding, Ii

Chee Lim Nge

Eugene Gorbatov

Naoki Matsumura

Tod F Schiff

Xiaoguo Liang

Jorge Pedro Rodriguez

Andy Keates

Don J Nguyen

Hong W Wong

Zhongsheng Wang

Patrick K Leung

Vasudevan Srinivasan

Tawfik M Rahal-Arabi

Philip R Lehwalder

Basavaraj B Astekar

Brian C Fritz

Gang Ji

Efraim Rotem

Jian Wang

Mark Angus MacDonald

Krishnan Ravichandran

Lilly Huang

Chia-Hung Sophia Kuo

Vivek Paranjape

Yifan Li

Tin-Cheung Kung

Nimrod Angel

Jenn Chuan Cheng

Matthew D Coakley

Doron Rajwan

Stephen H Gunther

Jun Zhang

Xiang Sean Zhou

Alexander Gendler

Robert A Dunstan

David W Browning

Nir Rosenzweig

Rajiv K Mongia

Harish Krishnamurthy

Andrew Keates

Darren S Crews

Michael Zelikson

Chung-Hao Chen

Alexander Lyakhov

George H Daskalakis

Sameer Shekhar

Wayne Proefrock

Christine Hana Kim

Sapumal Wijeratne

Jeffrey A Carlson

Arik Gihon

Muhammad Abozaed

Khondker Z Ahmed

Hue Lam

Jeffrey Krieger

Hee-Jun Park

Ameya Ambardekar

Mike Ngo

Gary L Bookhardt

Scot Lester

Vishram Shriram Pandit

Ashwin Umapathy

Jeffrey Jull

Allen Huang

Teal Hand

Thyagarajan Srinivasan

Sheng Ren

Jorege P Rodriguez

Sofia C Hao

Caren Magi

Ashwin Umpathy

Vikas Vij

Maytal Toledano

Jim Xu

Vivek Ramani

Huaping Jiang

A driver (e.g., a firmware or software) that improves the performance of the system-on-chip (SoC) in battery mode. The driver is a Peak Power Manager (PPM) which allows drastically higher SoC peak power limit levels (and thus higher Turbo performance) in battery mode. The PPM sets the Vth threshold voltage (the voltage level at which the platform will throttle the SoC) in such a way as to prevent the system from unexpected shutdown (or black screening). The PPM calculates the Psoc,pk SoC Peak Power Limit (e.g., PL4), according to the threshold voltage (Vth). These are two dependent parameters, if one is set, the other can be calculated. The scheme by the PPM is used to optimally set one parameter (Vth) based on the system parameters, and the history of the operation.

Processor peak current control apparatus and method

Peak power setting circuitry is provided to set a peak power value for an integrated circuit device. A power supply interface is to receive a value to estimate a peak power capacity of a power supply serving the integrated circuit device and processing circuitry is provided to calculate an approximate peak power for the integrated circuit device. A peak power for the integrated circuit device is determined by increasing the approximate peak power depending on an amount by which the integrated circuit device power is reduced in response to assertion of a throttling signal.

Peak power determination for an integrated circuit device

A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Digital linear regulator clamping method and apparatus

Techniques and mechanisms for supplementing power delivery with a battery. In an embodiment, a voltage is provided at a first node with the battery to power a load circuit. A charger is coupled between the first node and a second node, wherein a capacitor is coupled to provide charge to the charger via the second node. In response to detecting a transition of the voltage below a threshold voltage level, controller logic operates switch circuitry of the charger to provide charge from the capacitor. Such operation maintains the voltage in a range of voltage levels which are each above a minimum voltage level required by the load. At least a portion of the range is below the threshold voltage level. In some embodiments, another voltage at the second node provides a basis for generating a control signal to throttle an operation of the load circuit.

Voltage minimum active protection circuit and method of operating same

An apparatus is provided which comprises: a first circuitry to estimate variation of an internal impedance of a battery; a second circuitry to estimate a high power that the battery can supply for a first time-period, based on the estimated variation of the impedance of the battery; and a third circuitry to facilitate operation of one or more components of the apparatus in accordance with the estimated high power for the first time-period.

Dynamic battery power management based on battery internal impedance

A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 &#x3bc;S) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).

Fast dynamic capacitance, frequency, and/or voltage throttling apparatus and method

When power is provided through a USB-C cable from a source device to a sink device, a sudden connection or disconnection of the cable between the two devices may cause a sudden power surge or power drop in at least one of those devices, leading to other problems. To avoid this sudden event from causing potential damage or disruption to one of the devices, in some embodiments a CC pin in the cable is used to announce the impending connection/disconnection, and the device may throttle back its power consumption before power is actually applied to or removed from the power pins.

USB type-C power delivery management

An embodiment of a semiconductor package apparatus may include technology to determine history information for a battery, predict a peak power capacity of the battery based on the history information, and set a peak power parameter based on the predicted peak power capacity.

History based peak power prediction

Systems, apparatuses and methods may provide for technology that supplements a battery coupled to a processor configuration with stored energy from a charger input, wherein the battery is supplemented with the stored energy in response to an increased power demand on the battery. The technology may also initiate one or more throttle operations in the processor configuration if the increased power demand does not end before the stored energy is depleted. If the increased power demand ends before the stored energy is depleted, the one or more throttle operations may be bypassed. The increased power demand may correspond to a system voltage being below a voltage threshold, a battery current being above a current threshold, and so forth.

Supporting maximum power spikes above battery capability without throttling

In some examples, a peak power system includes a plurality of system components, one or more of the system components to dynamically provide a peak power requirement of the component. The system also includes a peak power manager to receive the peak power requirement of the one or more of the system components. The peak power manager can also dynamically provide, based on a system peak power limit and based on at least one updated peak power requirement received from at least one of the one or more system components, an updated component peak power limit to one or more of the system components.

Power management and protection

Systems, apparatuses, and methods may include a first power source to output power at a first normal power level and a first peak power level and a second power source cooperating with the first power source to output power at a second normal power level and a second peak power level. A system peak power control unit may monitor workload power requirements and cause the first power source to output the first peak power level at a first time period and cause the second power source to output the second peak power level at a second time period, different from the first time period. The time periods may be contiguous or discontiguous.

Peak power control and sequencing for multiple power supplies

Various embodiments may be generally directed to techniques for using an observed battery stress history to manage operation of a computing system component in a high power performance mode when powered by a battery. Various embodiments include techniques for tracking stresses to a battery. Various embodiments include techniques for comparing the battery stress history to a degradation baseline for the battery. Various embodiments include techniques for developing a degradation baseline for a battery including, for example, a degradation baseline based on expected stress to a battery and/or a degradation baseline based on a battery reliability model. Various embodiments include techniques for determining a battery stress surplus or deficit. Various embodiments include techniques for managing operation of a performance enhancing mode or high power performance mode of a computing system component based on the determined battery stress surplus or deficit.

Battery reliability odometer

One embodiment provides an apparatus. The apparatus includes power control logic and a critical comparator. The power control logic is to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin). The critical comparator is to compare a system power consumption value (Psys) and the critical threshold and to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.

System power management

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Hillsboro, OR, United States of America

Alexander Uan-Zo-Li