Infineon Technologies Ag

Alexander Trüby

Klaus-Dieter Morhard

Ulrich Zimmermann

Andreas Rusch

Mark Hollatz

Yoichi Otani

Dirk Többen

Steffen Rothenhäusser

A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in the semiconductor memory elements, An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.

Method of making a semiconductor memory device

The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA'; AA&#x2033;;) are provided. said sub-structures (STI; AA; AA&#x2032;; AA&#x2033;,) having a first sub-structure (AA&#x2032;) with planar regions (PS) and first trench regions (DT). A layer to be planarized is applied over the semiconductor structure, said layer having appropriate recesses above the first trench regions (DT) of the first sub-structure (AA&#x2032;). The method comprises the following steps: pre-planarization of the layer to be planarized by an etching step, using a pre-planarization mask, then subsequent planarization of the layer to be planarized by a chemical-mechanical polishing step. According to the invention, a first region (B) is formed on the layer to be planarized above the first sub-structure (AA&#x2032;) by means of the pre-planarization mask, said region having a predetermined grid of masked and unmasked sections (M; O) are arranged in such a way that they respectively cover both first trench regions (DT) and planar regions (PS), and a supporting structure for the chemical-mechanical polishing step, which corresponds with the masked sections (M) of the grid, is created by the etching step, using the pre-planarization mask.

Method for the planarization of a semiconductor structure

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Dresden, Germany

Alexander Trüby