Lsi Logic Corporation

Lsi Corporation

Intel Corporation

Lis Logic Corporation

Alexander S Podkolzin

Ranko L Scepanovic

James S Koford

Alexander E Andreev

Stanislav V Aleshin

Edwin R Jones

Valeriy B Kudryavtsev

Michael D Rostoker

Gobi R Padmanahben

Ashok K Kapoor

Elyar Eldarovich Gasanov

Andrej A Zolotykh

Valery B Kudryavtsev

Valeriv B Kudryavtsev

Lav D Ivanovic

Sergey Afonin

Anatoli Aleksandrovich Bolotov

Mikhail I Grinchuk

Edward M Roseboom

Shaohua Yang

Douglas B Boyle

Alexei Vladimirovich Galatenko

Valeriy B Kudryavstev

Valery D Kudryavtsev

Ashook K Kapoor

Valeriy B Kudryvavtsev

Valerity B Kudryavtsev

Disclosed is a method and apparatus for matching regular expressions. A buffer of symbols giving a number of the last occurrence positions of each symbol is maintained. When two constants match on either side of a regular expression operator, the buffer of symbols is queried to determine if a member of the complement of the regular expression operator occurred between the two constants. If so, then the operator was not satisfied. If not, then the operator was satisfied.

Impulse regular expression matching

A method for finding a valid codeword based on a near codeword trapping in a low-density parity-check decoding process includes identifying trapping set configurations and applying corrections to produce trapping sets with a limited number of invalid checks. Trapping set configurations are corrected in order to produce a trapping set in a table of trapping sets, the table associating each corrected trapping set with a valid codeword.

Majority-tabular post processing of quasi-cyclic low-density parity-check codes

The present invention is directed to a method and apparatus to find an optimal unification substitution for formulas in a technology library. In an exemplary aspect of the present invention, a method for finding an optimal unification substitution for formulas in a technology library during integrated circuit design may include the following steps: (a) receiving input including a list L of pairs of formulas in standard form, a set S of substitutions for variables, a right part e(x, . . . , x) of an identity, and an information I={t, h, r, a, p} on best application; (b) when the list L is not empty, extracting and removing first pair (&#x192;'(A&#x2032;, . . . , A&#x2032;), g&#x2032;(B&#x2032;, . . . , B&#x2032;)) from the list L; (c) removing head inverters and buffers from formulas &#x192;&#x2032;(A&#x2032;, . . . , A&#x2032;) and g&#x2032;(B&#x2032;, . . . , B&#x2032;)) and obtaining a pair (&#x192;(A, . . . , A), g(B, . . . , B)); (d) when the &#x192; is a commutative operation but neither a variable nor constant, and when heads of the formulas &#x192;(A, . . . , A) and g(B, . . . , B) are equal, searching for a basic argument Aof the formula &#x192;(A, . . . , A); (e) when the basic argument Ais found, letting P be head of said Aand setting i=1; (f) when head of Bis equal to the P, making copy L&#x2032; of the list L and making copy S&#x2032; of the set S; and (g) forming a reduced pair (A&#x2032;, B&#x2032;) for pairs (&#x192;(A, . . . , A), &#x192;(B, . . . , B)) and (A, B) and adding the pairs (A, B) and (A&#x2032;, B&#x2032;) to the list L&#x2032;.

Method and apparatus for finding optimal unification substitution for formulas in technology library

Integrated circuits are designed having optimal signal timing between and among cells. A set of identities are generated corresponding to logic operations and to library cells in technology basis. A resynthesis window is created for the identities having less than a predetermined depth of critical variables. Logic equations of the resynthesis window are transformed using the identities, and the resynthesized window area is optimized.

Method and apparatus for optimizing the timing of integrated circuits

The present invention includes methods for optimizing integrated circuit design by identifying a buffer tree in the integrated circuit design, the buffer tree having a plurality of vertices, each representing one of a buffer and an inverter, and also having branches, between the vertices, each representing an electrical connection. A plurality of optimization devices are applied in a random sequence to the vertices of the buffer tree. Such devices can include, for example, cell type modification; insertion of one buffer; insertion of several buffers; interchange of two grandchildren; making a grandchild into a child; making a child a grandchild; interchanging a child and a grandchild; eliminating two inverters; removing one buffer; removing more than one buffer; and removing two inverters.

Method and apparatus for dynamic buffer and inverter tree optimization

The present invention is a method for searching an identity base for identities that can be applied to a given formula. The method includes transforming the formulas from an identity base into a standard form, creating a set of code words for said identity base, constructing a lexicographical tree of a code word set of said identity base, and outputting a list of formula numbers from said identity base.

Method and apparatus for quick search for identities applicable to specified formula

The present invention comprises method for optimizing an integrated circuit design that includes computing of capacities and delays of an integrated circuit design, resynthesizing said integrated circuit design utilizing a plurality of local optimization procedures, and removing overlap the local optimization procedures can include a local resynthesis of logic trees procedure that utilizes multiple cost functions, a dynamic buffer and inverter tree optimization procedure, and a cell resizing procedure. Generally, faster local optimization procedures are applied first and slower, more thorough procedures are applied to areas where the faster procedures have not solved the optimization tasks.

Method and apparatus for timing driven resynthesis

Provided are systems and techniques for optimizing an integrated circuit design, in which a critical zone is identified in an integrated circuit design and a plurality of alternative identities are applied in the critical zone in order to obtain a corresponding plurality of outcomes. Alternative representations are then identified as those of the plurality of outcomes pursuant to which at least one of ramptime and timing are improved, and a best one of the alternative representations is selected to replace into the critical zone based on specified priorities which include: (i) selecting based on reduction in ramptime violation; (ii) selecting from among alternative representations that preserve cell area based on timing improvement; and (iii) if all alternative representations increase cell area, selecting based on an evaluation of a relationship between timing decrement and area increment.

Method and apparatus for local resynthesis of logic trees with multiple cost functions

The present invention selects parts of an integrated circuit description for resynthesis and then prepares those parts for resynthesis. Initially, a resynthesis goal is input, with the resynthesis goal having been selected from a set of possible resynthesis goals. Plural buffer and/or logic trees in the integrated circuit description are then selected based on the resynthesis goal, and information for each of the selected trees is obtained and stored. The tree information includes: (i) a description of each tree cell, including cell types, cell coordinates, and flips and angles of the tree cell, (ii) a description of each input net, (iii) a signal arrival time for each input net as a function of a capacity of such input net, (iv) coordinates of each pin driving each input net, and (v) a maximum capacity of each input net that will prevent such input net from having a timing violation.

Method and apparatus for optimal critical netlist area selection

Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60&deg;. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a &ldquo;tri-ister&rdquo; is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.

Hexagonal architecture

Programmable triangular shaped device having variable gain

A process for designing an integrated circuit chip includes specifying a set of cells, a set of wiring nets for interconnecting the cells, and a set of regions on the chip in which the cells are to be placed. An assignment of the cells of the set to the regions is generated, and the set of cells is randomly divided into a first subset of cells which remain in the assignment, and a second subset of cells which are removed from the assignment. Penalties are computed for assigning the cells of the second subset to the regions respectively, and the cells of the second subset are assigned to the regions such that a total penalty thereof is minimized. The process is repeated iteratively with the size of the second subset being progressively reduced relative to the size of the first subset until an end criterion is reached.

Physical design automation system and process for designing integrated

Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a 'tri-ister' is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.

Growing community of inventors

Moscow, Russia

Alexander S Podkolzin