Altera Corporation

Alexander Rusakov

Alexander Andreev

Eng Huat Lee

Andrei Nikishin

Alexander Yakhontov

A circuit design system is configured to generate a circuit design for an integrated circuit. The circuit design system includes a placement tool configured to generate a graph comprising flows between objects in a first level of a pyramid and targets in the first level. The placement tool generates clusters of objects in a second level of the pyramid in each of the objects in the first level. The objects in the first and the second levels comprise circuit blocks in the circuit design. The placement tool generates clusters of targets in the second level of the pyramid in each of the targets in the first level. The targets in the first and the second levels include subregions of the integrated circuit. The placement tool generates flows from the objects in the second level to the targets in the second level for a placement of the circuit blocks.

Systems and methods for generating placements for circuit designs using pyramidal flows

An integrated circuit includes a clock macro circuit. The clock macro circuit includes first, second, and third latch circuits and a multiplexer circuit. The first latch circuit is coupled to the second latch circuit. The multiplexer circuit is coupled to the second and third latch circuits. The clock macro circuit includes programmable vias that are programmed during fabrication of the integrated circuit to couple inputs of the clock macro circuit to the first latch circuit, the second latch circuit, the third latch circuit, and the multiplexer circuit. Programming the programmable vias causes the clock macro circuit to function as a selected type of clock circuit.

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Moscow, Russia

Alexander Rusakov