Acuid Corporation Limited

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Acuid Corporation (guernsey) Limited

Memory Corporation Plc

Jabra Corporation

Memory Corporation Technology Limited

Patentica IP Ltd

Alexander Roger Deas

Igor Anatolievich Abrosimov

Vasily Grigorievich Atyunin

David Coyne

Boris Nikolaevich Vilkov

Gordon Faulds

Ilya Valerievich Klotchkov

Vladimir Nikolayevich Davydov

Vadim Sergeyevich Demidov

Alexey Nikolaevich Bogatchev

Ilya Vasilievich Klotchkov

Marat Vadimovich Evtukhov

Igor Anatolievich Abrossimov

An improvement in the security of a logic system by minimizing observable features such as the power supply or electromagnetic radiation, so called, 'side-channel attacks'. Specifically, the present invention comprises a technique and methods for reducing the ability of an intruder to monitor the relationship between currents in the system and the data in the system through the use of a randomized clock wherein the clock eye diagram is closed and without significant reduction in maximum operating speed compared to the reduction in maximum operating frequency that occurs when using conventional means of additive jitter. A system where the clock eye diagram is completely closed is provably more secure than systems where the clock eye diagram is partially open.

Logic system with resistance to side-channel attack by exhibiting a closed clock-data eye diagram

Bidirectional differential point to point simultaneous high speed signalling is provided between integrated circuits with highly effective echo canceling. Each integrated circuit comprises a transmitter for transmitting a first signal to another integrated circuit and a receiver for receiving a second signal from the other integrated circuit. The transmitter has an output buffer; a receiver has a receiver buffer and is co-located on the same integrated circuit; and a differential buffer is coupled between the input of the transmitter buffer and the output of the receiver buffer. To increase the quality of receiving the second signal, a third signal adjusted in phase and amplitude is coupled at the output of the receive buffer, so that the echoing of the first signal is canceled. Preferably, the rise time of the third signal is also adjusted.

Simultaneous bidirectional differential signalling interface

A reference voltage generator and a method for generating a reference voltage for a logic device using the reference voltage generator is provided. The voltage reference generator includes a ring oscillator having a plurality of logic gates and a phase/frequency detector. A first reference voltage is generated on the basis of a phase/frequency difference between the phase/frequency of a reference clock and the phase/frequency of the ring oscillator. A second reference voltage is generated on the basis of a voltage swing of the oscillator circuit. Both reference voltages can be applied to the plurality of logic gates of the ring oscillator such that a constant delay is created through each logic gate of the logic device.

Reference voltage generator for logic elements providing stable and predefined gate propagation time

A data transmission apparatus and method employing the phase noise characteristics within the receiving registers to measure and control the characteristics of the channel as a function of the data pattern and to compensate for production tolerances within the channel by altering the timing characteristics of the signal at either the transmitter or receiver as a function of the data. Time offsets between different signals that form the communication channel are measured for different frequencies and/or for different data patterns transmitted through the channel and stored to compensate for an inter-signal skew by performing relative alignment of the measured offsets to a main clock edge.

Data transmission apparatus for high-speed transmission of digital data and method for automatic skew calibration

An amplifier circuit for receiving an input signal and providing an output signal, comprises a main chain of logic stages with a plurality of nodes therebetween, and at least one auxiliary chain nested between one node in the main chain and another node, which is not the next node, to form a series of feed back or feed forward nested equalisation loops; whereby the input signal is fed serially down the main chain and is also fed through the said at least one auxiliary chain and summed to provide the output signal. The invention overcomes gain-bandwidth limits of the drive stages and bandwidth reductions that occur when analogue stages operating in a linear mode are concatenated.

High speed amplifier incorporating pre-emphasis

The present invention relates to high speed communications, in particular, to an interface device between a transmitting device and a receiving device of a transmission system, wherein the transmitting device is capable of automatic compensation of cross-talk timing errors in the interface device, for a group of signals, by using information stored in a storage attached to that interface device. Preferably, the data stored in said storage comprises data on interconnections between said first and second plurality of terminals and data on crosstalk timing errors in said transmission lines relating to a specific data pattern, for each of said stored interconnection.

Interface device with stored data on transmission lines characteristics

A means for reducing the power consumption of the transmitter by storing the recent history of the transmitted data using a string of gates with taps from the string taken at points determined by the propagation delay of each gate and controlling driving transistors as a function of comparison of that history with input data so that, either the signal is driven into the transmission line at full strength, or at a level near the minimum needed to retain the state in the receiver. The advantage of the invention is that the line capacitance decays through the terminating resistors or discharge transistors, such that when the next state change is needed, then line has less stored energy needing to be discharged.

Line driver with reduced power consumption

The present invention relates to the reduction of artifacts introduced by sending data at a higher rate than the bandwidth of the communication channel, such as the voltage and current offsets introduced in the data at the receiver as a function of the preceding data.

Means and method of data encoding and communication at rates above the channel bandwidth

The present invention relates in general to the field of generation of precise electrical signals, in particular, to a technique for providing accurate delays of signals using a controllable delay line, and is applicable to the areas of high speed communication and memory testing equipment. According to the present invention, an auxiliary reference channel having a delay line which is identical to the main delay line is incorporated into vernier silicon die to allow automatic adjustment of the delay in the main delay line using a reference periodical signal applied to the auxiliary delay line.

Programmable self-calibrating vernier and method

A timing control device and method for minimizing timing uncertainties due to skew and jitter, wherein a device for the compensation of timing errors in multiple channel electronic devices comprises at least one register having a plurality of channels comprising: a clock for providing a clock signal; a reference signal generator for generating reference signals for deskewing the registers. For each register, a corresponding feedback loop is associated for the relative alignment of the register's timing. The feedback loop comprises a device for detecting a deviation from a predetermined level of probability of reading by the register of a desired symbol on a boundary of two reference channel symbols in a sequence, and a set of delay devices which use the detected values of probability to generate a feedback signal.

Timing control means for automatic compensation of timing uncertainties

Self-contained underwater re-breathing apparatus

A high speed communication apparatus with means for reducing timing uncertainty providing a high accuracy of transferring and receiving signals by intelligent skew calibration of the apparatus. The system for reducing timing uncertainty of a communication apparatus comprises a plurality of driving registers for transmitting signals; a plurality of receiving registers for receiving signals; a main clock for generating a main clock signal; a reference clock for generating reference signals for calibrating the registers; and a plurality of phase shift means comprising at least one set of phase shift means associated with each said plurality of registers, for the relative alignment of the register's timing within each plurality. The apparatus preferably further comprises a storage means for recording and storing information on skew in a communication media, for at least one data pattern transmitted through the transmission line and a plurality of adjustment means for generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the information stored in the storage means, so as to compensate the above skew.

Skew calibration means and a method of skew calibration

The present invention relates to a transmitter for high speed communication systems, comprising a plurality, preferably two, drivers each having series terminating resistor, wherein the series terminating resistors are joined at the transmission line. The drivers are controlled in two modes. In the first mode, a control unit supplies drivers with a signal which is a function of input data, to provide the transmitter drives a communication line with an output impedance equal to the parallel effect of all the terminating resistors. In the second mode, the control unit generates a signal to make the drivers with respective series terminating resistors acting as a parallel termination circuit. No actual data is transmitted in this mode. In a preferable embodiment, to achieve this, one driver or a group of drivers drives one logic level signal, while the other drivers drives the inverse to this signal.

Transmitter with active differential termination

A high precision receiver with a means to reduce or compensate the skew caused by the receiver's hysteresis by using a dynamic reference that is varied depending on a current output signal. To avoid oscillation, the reference signal can be switched over with a certain delay.

High precision receiver with skew compensation

A method for producing a probe unit for contacting an electronic circuit such as a wafer or a die having a predetermined pattern of contact pads deployed in a common plane. The method employes a base plate of made of a material capable of surface uplift when irradiated. On the surface of the base plate locations corresponding to said contact pads are determined. Further, the base plate is irradiated at the determined locations by means of a laser. This results in forming conical surface uplifts. The method further includes plating the conical surface uplifts with an electrically conductive material and providing means for electical connection between said plated conical surface uplifts and an external device.

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Edinburgh, United Kingdom

Alexander Roger Deas