Infineon Technologies Ag

Infineon Technologies Dresden Gmbh & Co . Kg

Infineon Technologies Austria Ag

Alexander Philippou

Johannes Georg Laven

Christian Jaeger

Antonio Vellei

Roman Baburske

Frank Dieter Pfirsch

Matteo Dainese

Francisco Javier Santos Rodriguez

Markus Beninger-Bina

Caspar Leendertz

Markus Bina

Christian Philipp Sandow

Erich Griebl

Hans-Joachim Schulze

Anton Mauder

Ingo Dirnstorfer

Helmut Maeckel

Franz-Josef Niedernostheide

Max Christian Seifert

Franz Hirler

Hans-Juergen Thees

Frank Wolter

Maria Cotorogea

Dorothea Werber

Christian Robert Mueller

Vera Van Treek

Thomas Mülders

Thorsten Arnold

Judith Specht

Ilaria Imperiale

A power semiconductor device having a barrier region is provided. A power unit cell of the power semiconductor device has at least two trenches that may both extend into the barrier region. The at least two trenches may both have a respective trench electrode coupled to a control terminal of the power semiconductor device. For example, the trench electrodes are structured to reduce the total gate charge of the power semiconductor device. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by the drift region. The barrier region can be electrically floating.

Power semiconductor device with dV/dt controllability and low gate charge

A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current.

Power semiconductor device having a barrier region

A power semiconductor device first trench structures extending from a first main surface into a semiconductor body up to a first depth. The first trench structures extend in parallel along a first lateral direction. Each first trench structure includes a first dielectric and a first electrode. The power semiconductor device further includes second trench structures extending from the first main surface into the semiconductor body up to a second depth that is smaller than the first depth. The second trench structures extend in parallel along a second lateral direction and intersect the first trenches at intersection positions. Each second trench structure includes a second dielectric and a second electrode. The second dielectric is arranged between the first electrode and the second electrode at the intersection positions.

Power semiconductor device including first and second trench structures

An power semiconductor device having a barrier region is provided. A power unit cell of the power semiconductor device has at least two trenches that may both extend into the barrier region. The at least two trenches may both have a respective trench electrode coupled to a control terminal of the power semiconductor device. For example, the trench electrodes are structured to reduce the total gate charge of the power semiconductor device. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by the drift region. The barrier region can be electrically floating.

A power semiconductor switch includes an active cell region with a drift region, an edge termination region, and IGBT cells within the active cell region. Each IGBT cell includes trenches that extend into the drift region and laterally confine mesas. At least one control trench has a control electrode for controlling the load current. At least one dummy trench has a dummy electrode electrically coupled to the control electrode. At least one further trench has a further trench electrode. At least one active mesa is electrically connected to a first load terminal within the active cell region. Each control trench is arranged adjacent to no more than one active mesa. At least one inactive mesa is adjacent to the dummy trench. A cross-trench structure merges each control trench, dummy trench and further trench to each other. The cross-trench structure overlaps at least partially along a vertical direction with the trenches.

Power semiconductor switch having a cross-trench structure

A method of processing a power semiconductor device includes: providing a semiconductor body with a drift region of a first conductivity type; forming a plurality of trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement at the semiconductor body, the mask arrangement having a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; forming, below bottoms of the exposed trenches, a plurality of doping regions of a second conductivity type complementary to the first conductivity type; removing the mask arrangement; and extending the plurality of doping regions in parallel to the first lateral direction such that the plurality of doping regions overlap and form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.

Method of processing a power semiconductor device

A power semiconductor device includes an active cell region with a drift region of a first conductivity type, a plurality of IGBT cells arranged within the active cell region, each of the IGBT cells includes at least one trench that extends into the drift, an edge termination region surrounding the active cell region, a transition region arranged between the active cell region and the edge termination region, at least some of the IGBT cells are arranged within or extend into the transition region, a barrier region of a second conductivity type, the barrier region is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells and does not extend into the transition region, and a first load terminal and a second load terminal, the power semiconductor device is configured to conduct a load current along a vertical direction between.

IGBT with dV/dt controllability

A power device includes: a diode section; a semiconductor body; a drift region extending into the diode section; trenches in the diode section and extending along a vertical direction into the semiconductor body, two adjacent trenches defining a respective mesa portion in the semiconductor body; a body region in the mesa portions; in the diode section, a barrier region between the body and drift regions and having a dopant concentration at least 100 times greater than an average dopant concentration of the drift region and a dopant dose greater than that of the body region. The barrier region has a lateral structure according to which at least 50% of the body region in the diode section is coupled to the drift region at least by the barrier region, and at least 5% of the body region in the diode section is coupled to the drift region without the barrier region.

Diode with structured barrier region

An RC IGBT with an n-barrier region in a transition section between a diode section and an IGBT section is presented.

RC IGBT with an IGBT section and a diode section

A semiconductor die includes a semiconductor body having first and second active portions. The first active portion includes first source regions. The second active portion includes second source regions. A gate structure extends from a first surface into the semiconductor body and has a longitudinal gate extension along a lateral first direction. A first load pad and the first source regions are electrically connected. A second load pad and the second source regions are electrically connected. A gap laterally separates the first and second load pads. A lateral longitudinal extension of the gap is parallel to the first direction or deviates therefrom by not more than 60 degree. A connection structure electrically connects the first and second load pads. The connection structure is formed in a groove extending from the first surface into the semiconductor body and/or in a wiring layer formed on the first surface.

Semiconductor die, semiconductor device and IGBT module

A power transistor having a semiconductor barrier region is presented. A power unit cell of the power transistor has at least two trenches that may both extend into the semiconductor barrier region. The semiconductor barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by the drift region. The semiconductor barrier region can be electrically floating. Further, the at least two trenches may both increase in width along their respective extension into the semiconductor body.

Power transistor with dV/dt controllability and tapered mesas

A power semiconductor device includes an active region surrounded by an inactive termination region each formed by part of a semiconductor body. The active region conducts load current between first and second load terminals. At least one power cell has trenches extending into the semiconductor body adjacent to each other along a first lateral direction and having a stripe configuration that extends along a second lateral direction into the active region. The trenches spatially confine a plurality of mesas each having at least one first type mesa electrically connected to the first load terminal and configured to conduct at least a part of the load current, and at least one second type mesa configured to not conduct the load current. A decoupling structure separates at least one of the second type mesas into a first section in the active region and a second section in the termination region.

Power semiconductor device having a cross-trench arrangement

An IGBT having a barrier region is presented. A power unit cell of the IGBT has at least two trenches that may both extend into the barrier region. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by means of the drift region. The barrier region can be electrically floating.

IGBT having a barrier region

A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body coupled to a first load terminal and a second load terminal and comprising a drift region configured to conduct a load current between said terminals. The drift region comprises dopants of a first conductivity type. A source region is arranged in electrical contact with the first load terminal and comprises dopants of the first conductivity type. A channel region comprises dopants of a second conductivity. At least one power unit cell that includes at least one first type trench. The at least one power unit cell further includes a first mesa zone and a second mesa zone of the semiconductor body.

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Munich, Germany

Alexander Philippou