Infineon Technologies Ag

Siemens Aktiengesellschaft

Other

International Business Machines Corporation

Infineon Technologies North America Corp.

Alexander Michaelis

Stephan Kudelka

Helmut Horst Tews

Ulrike Gruening

Uwe Paul Schroeder

Oliver Genz

Jack Allan Mandelman

Jochen C Beintner

Brian S Lee

Ulrich Mantz

Raj Jammy

Carl John Radens

Ramachandra Divakaruni

Till Schloesser

Gary Bela Bronner

Larry Alan Nesbit

Wolfgang Bergner

Martin Popp

Rajiv M Ranade

Zvonimir Gabric

Uwe Schroeder

Oswald Spindler

Kristin Schupke

Bertrand Flietner

Daniel Koehler

Stephen Kudelka

Dirk Tobben

An apparatus and method for measuring feature sizes having form birefringence. The method includes providing a surface having surface features thereon; radiating the surface features with light having a first wavelength and a first polarization; measuring a reflected polarization of light having the first wavelength reflected from the surface features; rotating the surface features by rotating the surface to measure the reflected polarization of the reflected light having the first wavelength at least one new rotated position; radiating the surface features with light having a second wavelength and the first polarization; measuring a reflected polarization of light having the second wavelength reflected from the surface features; rotating the surface features by rotating the surface to measure the reflected polarization of the reflected light having the second wavelength at least one new rotated position; and correlating the reflected polarization from the light having the first and second polarizations to surface feature sizes.

Optical measurement system and method

A method for eching a recess in a polysilicon region of a semiconductor device by applying a solution of NH OH in water to the polysilicon.

Etch process for recessing polysilicon in trench structures

A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the < > crystallographic plane and another one of such planes being the < > plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the < > plane being oxidized at a higher rate than sidewalls in the < > plane producing silicon dioxide on the silicon nitride layer having thickness over the < > plane greater than over the < > plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the < > plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the < > plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the < > plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the < > plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.

Semiconductor structures and manufacturing methods

A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the <100> crystallographic plane and another one of such planes being the <1 10> plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the with substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the <110> plane being oxidized at a higher rate than sidewalls in the <100> plane producing silicon dioxide on the silicon nitride layer having thickness over the <110> plane greater than over the <100> plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the <100> plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the <110> plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the <100> plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the <110> plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.

A method for clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A barrier material is deposited above a node conductor of the storage capacitor. A layer of silicon is deposited over the barrier material. Dopant ions are implanted at an angle into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.

Single sided buried strap

A semiconductor device formed by a method for aligning a strap diffusion, in accordance with the invention, includes the steps of providing a trench in a substrate, the trench having a storage node formed therein including a buried strap on top of the storage node, and depositing a dopant rich material on the buried strap. A trench top dielectric is formed on the dopant rich material, and portions of the dopant rich material are removed above the trench top dielectric. Dopants are outdiffused from the dopant rich material into an adjacent region of the substrate to form the strap diffusion by forming a gate in an upper portion of the trench such that the strap diffusion is operatively disposed relative to the gate.

Self-aligned buried strap for vertical transistors

A method of using at least two insulative layers to form the isolation collar of a trench device, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide ) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer ( ) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate ( ) doping.

Integrated circuit trench device with a dielectric collar stack, and method of forming thereof

A method for forming an oxide collar in a trench, in accordance with the present invention, includes forming a trench in a silicon substrate, and depositing and recessing a nitride liner in the trench to expose a portion of the silicon substrate on sidewalls of the trench. An oxide is deposited selective to the nitride liner on the portion of the silicon substrate. Residue oxide is removed from surfaces of the nitride liner to form a collar in the trench.

Collar formation by selective oxide deposition

In accordance with the present invention, a method for expanding trenches includes the steps of forming a trench in a substrate, preparing surfaces withIn the trench by etching the surfaces with a wet etchant to provide a hydrogen terminated silicon surface and anisoropically wet etching the trench to expand the trench.

Method for expanding trenches by an anisotropic wet etch

A system and method of forming an electrical connection ( ) to the interior of a deep trench ( ) in an integrated circuit utilizing a low-angle dopant implantation ( ) to create a self-aligned mask over the trench. The electrical connection preferably connects the interior plate ( ) of a trench capacitor to a terminal of a vertical trench transistor. The low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material ( ) overlying or in the trench, leaving a self-aligned mask ( ) covering a portion of the trench, and the remainder of the trench exposed for further processing. Alternatively, an etch process alone, with selectivity between the doped and undoped regions, may be used to create the mask. The self-aligned mask then allows for the removal of selective portions of the materials in the trench so that a vertical trench transistor and a buried strap may be formed on only one side of the trench.

Method of forming a vertically oriented device in an integrated circuit

A method for forming a valve metal oxide for semiconductor fabrication in accordance with the present invention is disclosed and claimed. The method includes the steps of providing a semiconductor wafer, depositing a valve metal on the wafer, placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the valve metal to form a metal oxide when a potential difference is provided between the valve metal and the solution and processing the wafer using the metal oxide layer.

Low temperature oxidation of conductive layers for semiconductor fabrication

A method for fabricating a semiconductor device, in accordance with the present invention, includes the steps of providing a semiconductor wafer having exposed p-doped silicon regions and placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the exposed p-doped silicon regions to form an oxide on the exposed p-doped silicon regions when a potential difference is provided between the wafer and the solution.

Low temperature self-aligned collar formation

A method of forming a vertically-oriented device in an integrated circuit using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a portion of the trench perimeter (e.g., isolation collar ) is protected by a mask (e.g., polysilicon ), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall ( ) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide ) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.

Integrated circuit vertical trench device and method of forming thereof

A method of forming semiconductor devices in accordance with the present invention includes the steps of providing a deep trench in a substrate, the deep trench having a lower portion and forming a dielectric layer in the deep trench by lining the lower portion of the deep trench with a dielectric layer, the dielectric layer including titanium. A semiconductor device includes a substrate having a trench formed therein, a storage node formed in the trench and capacitively coupled to the substrate and a dielectric layer formed in the trench between the storage node and the substrate, the dielectric layer lining a lower portion of the trench wherein the dielectric layer includes titanium oxide.

Method of forming a trench capacitor using a rutile dielectric material

A vertical trench in a silicon wafer for use in forming the storage capacitor of a DRAM is etched by reactive ion etching in a manner to have a profile that has multiple waists. This profile is obtained by varying the rate of flow of coolant in the base member on which the silicon wafer is supported during the reactive ion etching to vary the temperature of the silicon wafer during the etching. Alternatively, the multiple waists are achieved by either by varying the ratio of the different gases in the etching chamber or the total gas pressure in the chamber.

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Wappingers Falls, NY, United States of America

Alexander Michaelis