International Business Machines Corporation

Alexander Michael Taft

Guy L Guthrie

Derek E Williams

Bernard Charles Drerup

Jeffrey A Stuecheli

Hugh Shen

Luke Murray

Sanjeev Ghai

Richard Nicholas

Luis E De La Torre

Joseph John McGill, Iv

The present disclosure may include a processor that uses idle caches as a backing store for a boot code. The processor designates a boot core and an active cache from a plurality of cores and a plurality of caches. The processor configures remaining caches from the plurality of caches to act as a backing store memory. The processor modifies the active cache to convert cast outs to a system memory into lateral cast outs to the backing store memory. The processor copies a boot image to the backing store memory and executes the boot image by the boot core.

Using idle caches as a backing store for boot code

A coherent data processing system includes a system fabric communicatively coupling a plurality of coherence participants and fabric control logic. The fabric control logic quantifies congestion on the system fabric based on coherence messages associated with commands issued on the system fabric. Based on the congestion on the system fabric, the fabric control logic determines a rate of request issuance applicable to a set of coherence participants among the plurality of coherence participants. The fabric control logic issues at least one rate command to set a rate of request issuance to the system fabric of the set of coherence participants.

Controlling issue rates of requests of varying broadcast scopes in a data processing system

A data processing system includes a plurality of processor cores each supported by a respective one of a plurality of vertical cache hierarchies. Based on receiving on a system fabric a cache injection request requesting injection of a data into a cache line identified by a target real address, the data is written into a cache in a first vertical cache hierarchy among the plurality of vertical cache hierarchies. Based on a value in a field of the cache injection request, a distribute field is set in a directory entry of the first vertical cache hierarchy. Upon eviction of the cache line the first vertical cache hierarchy, a determination is made whether the distribute field is set. Based on determining the distribute field is set, a lateral castout of the cache line from the first vertical cache hierarchy to a second vertical cache hierarchy is performed.

Distribution of injected data among caches of a data processing system

A data processing system includes system memory and a plurality of processor cores each supported by a respective one of a plurality of vertical cache hierarchies. A first vertical cache hierarchy records information indicating communication of cache lines between the first vertical cache hierarchy and others of the plurality of vertical cache hierarchies. Based on selection of a victim cache line for eviction, the first vertical cache hierarchy determines, based on the recorded information, whether to perform a lateral castout of the victim cache line to another of the plurality of vertical cache hierarchies rather than to system memory and selects, based on the recorded information, a second vertical cache hierarchy among the plurality of vertical cache hierarchies as a recipient of the victim cache line via a lateral castout. Based on the determination, the first vertical cache hierarchy performs a castout of the victim cache line.

Targeting of lateral castouts in a data processing system

A data processing system includes a plurality of snoopers, a processing unit including master, and a system fabric communicatively coupling the master and the plurality of snoopers. The master sets a retry operating mode for an interconnect operation in one of alternative first and second operating modes. The first operating mode is associated with a first type of snooper, and the second operating mode is associated with a different second type of snooper. The master issues a memory access request of the interconnect operation on the system fabric of the data processing system. Based on receipt of a combined response representing a systemwide coherence response to the request, the master delays an interval having a duration dependent on the retry operating mode and thereafter reissues the memory access request on the system fabric.

Data processing system having masters that adapt to agents with differing retry behaviors

A processor core is supported by an upper level cache and a lower level cache that receives, from an interconnect fabric, a write injection request requesting injection of a partial cache line of data into a target cache line identified by a target real address. In response to receipt of the write injection request, a determination is made that the upper level cache is a highest point of coherency for the target real address. In response to the determination, the upper level cache and lower level cache collaborate to transfer the target cache line from the upper level cache to the lower level cache. The lower level cache updates the target cache line by merging the partial cache of data into the target cache line and storing the updated target cache line in the lower level cache.

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Austin, TX, United States of America

Alexander Michael Taft