Lsi Corporation

Ascensia Diabetes Care Holdings Ag

Alexander Markovic

Ivan Leonidovich Mazurenko

Aleksey Alexandrovich Letunovskiy

Denis Vassilevich Parfenov

Qiang Fu

Joseph R Anstett, Jr

Vladislav Milenkovic

Alexander Alexandrovich Petyushko

Andrey Nikitin

Alexei Vladimirovich Galatenko

Ilya Viktorovich Lyalin

Dmitriy Vladimirovich Alekseev

Pavel Aleksandrovich Aliseychik

Denis Vladimirovich Parkhomenko

Dmitry Nikolaevich Babin

Some embodiments of the present invention include pairing two wireless devices by placing at least one of two devices in a pairing mode; performing at least one pairing motion event with at least one of the wireless devices to satisfy at least one pairing condition; detecting satisfaction of the at least one pairing condition; and pairing the two wireless devices in response to detecting satisfaction of the at least one pairing condition. Numerous other aspects are provided.

Device pairing taking into account at least one condition

In one embodiment, an acoustic echo control (AEC) module receives an outgoing signal and an incoming signal, which, at various times, contains acoustic echo corresponding to the outgoing signal. The AEC module has a delay estimation block that estimates, in the time domain, the echo delay using an adaptive filtering technique. This delay estimation is used to align samples of the incoming signal having acoustic echo with the corresponding samples of the outgoing signal from which the acoustic echo originated. The AEC module determines whether or not samples of the incoming signal contain acoustic echo based on the aligned outgoing signal, and the determinations are applied to a hangover counter. The AEC module then suppresses acoustic echo in the incoming signal and adds comfort noise to the incoming signal. The amount of echo suppression performed is gradually increased or decreased based on comparisons of the counter to a hangover threshold.

Time-domain acoustic echo control

A video transcoder for converting an encoded input video bit-stream having one spatial resolution into an encoded output video bit-stream having a lower spatial resolution, wherein learned statistics of intra-mode transcoding are used to constrain the search of intra modes for the output video bit-stream. The statistics of intra-mode transcoding can be gathered, e.g., by applying brute-force downsizing to a training set of video frames and then analyzing the observed intra-mode transcoding patterns to determine a transition-probability matrix for use during normal operation of the transcoder. The transition-probability matrix enables the transcoder to select appropriate intra modes for the output video bit-stream without performing a corresponding exhaustive full search, which advantageously reduces the computational complexity and processor load compared to those of a comparably performing prior-art video transcoder.

Intra-mode prediction for a video transcoder

In one embodiment, a DSP having four arithmetic logic units (ALUs) and able to have two read/write operations per clock cycle performs silence detection and tone detection for data frames containing samples of an audio signal. The ALUs are used together in parallel to process the samples in the data frames received by the DSP. A received data frame is filtered by the silence detection so that substantially silent frames are dropped and non-silent frames are further processed. In the tone detection, a filtered data frame is processed, four samples at a time, to determine the power of the signal at a given frequency, where the power determination is used to determine whether a given tone (i.e., a signal at a given frequency) is present in the data frame.

High-performance tone detection using a digital signal processor (DSP) having multiple arithmetic logic units (ALUs)

A video transcoder for converting a compressed input video bit-stream having one spatial resolution into a compressed output video bit-stream having a different spatial resolution in a manner that enables the transcoder to dynamically change the amount of computational resources allocated to the conversion process. In one embodiment, the video transcoder has a plurality of configurable processing paths whose configuration determines the amount of allocated computational resources. Exemplary processing-path configuration changes may include, but are not limited to engaging or disengaging a processing path, redirecting a data flow from flowing through one processing path to flowing through another processing path, and attaching or detaching one or more processing modules to an engaged processing path. The capability to make these and other configuration changes enables the video transcoder to adjust the computational complexity and picture quality on the fly, without interrupting the video sequence in the output video bit-stream.

Video transcoder with flexible quality and complexity management

A video transcoder for converting an encoded input video bit-stream having one spatial resolution into an encoded output video bit-stream having a lower spatial resolution, wherein motion-vector dispersion observed at the higher spatial resolution is quantified and used to configure the motion-vector search at the lower spatial resolution. For example, for video-frame areas characterized by relatively low motion-vector dispersion values, the motion-vector search may be performed over a relatively small vector space and with the use of fewer search patterns and/or hierarchical search levels. These constraints enable the transcoder to find appropriate motion vectors for inter-prediction coding without having to perform an exhaustive motion-vector search for these video-frame areas, which advantageously reduces the computational complexity and processor load compared to those of a comparably performing prior-art video transcoder.

Motion estimation for a video transcoder

In one embodiment, a cryptography processor compatible with the Advanced Encryption Standard (AES) for encrypting and decrypting has a memory storing each element of an AES State, normally 8-bit long, in a corresponding memory space that is at least 9 bits long. Using the larger memory spaces, the processor performs modified AES transformations on the State. A modified column-mixing transformation uses bit-shifting and XOR operations, thereby avoiding some multiplications and modulo reductions and resulting in some 9-bit State elements. A modified byte-substitution transformation uses a 512-element look-up table to accommodate 9-bit inputs. The modified byte-substitution transformation is combined with a modified row-shifting transformation. The memory has data registers each holding four State elements. A modified expanded key schedule is used in a modified round-key-adding transformation that is combined with the modified column-mixing transformation, wherein all four elements stored in a single data register are processed together in some operations.

Cryptographic processing using a processor

In certain embodiments, a digital signal processor (DSP) has multiple arithmetic logic units and a register module. The DSP is adapted to generate a message digest H from a message M in accordance with the SHA-1 standard, where M includes N blocks M, i=1, . . . , N, and the processing of each block Mincludes t iterations of processing words of message schedule {W}. In each iteration possible, the DSP uses free operations to precalculate Wand working variable values for use in the next iteration. In addition, in each iteration possible, the DSP rotates the registers associated with particular working variables to reduce operations that merely copy unchanged values from one register to another.

Growing community of inventors

Media, PA, United States of America

Alexander Markovic