International Business Machines Corporation

Alexander L Martin

Eric Peter Solecky

Karen Lynne Holloway

Roger J Yerdon

Timothy J Wiltshire

Martin E Powell

Holly A LaFerrara

A method and apparatus includes an integrated circuit device, and at least one alignment mark on the integrated circuit device, the alignment mark comprises a first coded region, a second coded region adjacent the first coded region, and a third coded region adjacent the second coded region, the second coded region located between the first coded region and the third coded region, and markings on the first coded region and the third coded region being identical.

Method for providing rotationally symmetric alignment marks for an alignment system that requires asymmetric geometric layout

A method for reducing edge effect interference with critical dimension (CD) measurement of semiconductor via structures includes forming a test structure in a kerf region of a semiconductor wafer, the test structure including at least a via structure and a trench structure in contact with the via structure. The via structure is formed in accordance with a critical dimension associated with a corresponding via structure in a circuit region of the semiconductor wafer, and the trench structure is formed in accordance with a widened dimension with respect to a minimum ground rule dimension associated with a corresponding trench structure in a circuit region of the semiconductor wafer.

Structure for reducing prior level edge interference with critical dimension measurement

Method and structure for reducing prior level edge interference with critical dimension measurement

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Hopewell Junction, NY, United States of America

Alexander L Martin