Silicon Storage Technology, Inc.

Alexander Kotov

Viktor Markov

Xian Liu

Jong-Won Yoo

Hung Quoc Nguyen

Yuri Tkachev

Tho Ngoc Dang

Thuan Vu

Amitay Levi

Jack Frayer

Chien-Sheng Su

Eugene Jinglun Tam

Michael James Heinz

Jung Hee Yun

Michael K Doan

Yuniarto Widjaja

Nhan Do

Sang Thanh Nguyen

Yaw Wen Hu

James Yingbo Jia

Loc Bao Hoang

Steven Lemke

Jinho Kim

Xiaozhou Qian

Steve Choi

Pavel Klinger

Xiao Yan Pi

Chien Sheng Su

James Cheng

Dmitry Bavinov

Satish Bansal

Steven Malcolm Lemke

A memory device and method for a non-volatile memory cell having a gate that includes programming the memory cell to an initial program state corresponding to a target read current and a threshold voltage, including applying a program voltage having a first value to the gate, storing the first value in a memory, reading the memory cell in a first read operation using a read voltage applied to the gate that is less than the target threshold voltage to generate a first read current, and subjecting the memory cell to additional programming in response to determining that the first read current is greater than the target read current. The additional programming includes retrieving the first value from the memory, determining a second value greater than the first value, and programming the selected non-volatile memory cell that includes applying a program voltage having the second value to the gate.

Method of improving read current stability in analog non-volatile memory by post-program tuning for memory cells exhibiting random telegraph noise

A method for screening memory cells includes erasing the memory cells, weakly programming the memory cells to a modified erased state, performing a first read operation on the memory cells after the erasing and the weakly programming, screening any of the memory cells that exhibit a read current during the first read operation below a margin read current threshold M, baking the memory cells after the first read operation, performing a second read operation on the memory cells after the baking, and screening any of the memory cells that exhibit a read current during the second read operation below the margin read current threshold M

Method of screening non-volatile memory cells

A method of programing a memory device having a plurality of memory cell groups where each of the memory cell group includes N non-volatile memory cells, where N is an integer greater than or equal to 2. For each memory cell group, the method includes programming each of the non-volatile memory cells in the memory cell group to a particular program state, performing multiple read operations on each of the non-volatile memory cells in the memory cell group, identifying one of the non-volatile memory cells in the memory cell group that exhibits a lowest read variance during the multiple read operations, deeply programming all of the non-volatile memory cells in the memory cell group except the identified non-volatile memory cell, and programming the identified non-volatile memory cell in the memory cell group with user data.

Method of reducing random telegraph noise in non-volatile memory by grouping and screening memory cells

A method and device for programming a non-volatile memory cell, where the non-volatile memory cell includes a first gate. The non-volatile memory cell is programmed to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the non-volatile memory cell. The target threshold voltage corresponds to a target read current. The non-volatile memory cell is read in a first read operation using a read voltage applied to the first gate of the non-volatile memory cell that is less than the target threshold voltage to generate a first read current. The non-volatile memory cell is subjected to additional programming in response to determining that the first read current is greater than the target read current.

Method of improving read current stability in analog non-volatile memory by program adjustment for memory cells exhibiting random telegraph noise

A memory device that includes a plurality of non-volatile memory cells and a controller. The controller is configured to erase the plurality of memory cells, program each of the memory cells, and for each of the memory cells, measure a threshold voltage applied to the memory cell corresponding to a target current through the memory cell in a first read operation, re-measure a threshold voltage applied to the memory cell corresponding to the target current through the memory cell in a second read operation, and identify the memory cell as defective if a difference between the measured threshold voltage and the re-measured threshold voltage exceeds a predetermined amount.

Method of improving read current stability in analog non-volatile memory cells by screening memory cells

A method of improving stability of a memory device having a controller configured to program each of a plurality of non-volatile memory cells within a range of programming states bounded by a minimum program state and a maximum program state. The method includes testing the memory cells to confirm the memory cells are operational, programming each of the memory cells to a mid-program state, and baking the memory device at a high temperature while the memory cells are programmed to the mid-program state. Each memory cell has a first threshold voltage when programmed in the minimum program state, a second threshold voltage when programmed in the maximum program state, and a third threshold voltage when programmed in the mid-program state. The third threshold voltage is substantially at a mid-point between the first and second threshold voltages, and corresponds to a substantially logarithmic mid-point of read currents.

Method of improving read current stability in analog non-volatile memory using final bake in predetermined program state

A memory device having non-volatile memory cells and a controller. In response to a first command for erasing and programming a first group of the memory cells, the controller determines the first group can be programmed within substantially 10 seconds of their erasure, erases the first group, and programs the first group within substantially 10 seconds of their erasure. In response to a second command for erasing and programming a second group of the memory cells, the controller determines that the second group cannot be programmed within substantially 10 seconds of their erasure, divides the second group into subgroups of the memory cells each of which can be programmed within substantially 10 seconds of their erasure, and for each of the subgroups, erase the subgroup and program the subgroup within substantially 10 seconds of their erasure.

Method of improving read current stability in analog non-volatile memory by limiting time gap between erase and program

A memory device with memory cells each including source and drain regions with a channel region there between, a floating gate over a first channel region portion, a select gate over a second channel region portion, a control gate over the floating gate, and an erase gate over the source region. Control circuitry is configured to, for one of the memory cells, apply a first pulse of programming voltages that includes a first voltage applied to the control gate, perform a read operation that includes detecting currents through the channel region for different control gate voltages to determine a target control gate voltage using the detected currents that corresponds to a target current through the channel region, and apply a second pulse of programming voltages that includes a second voltage applied to the control gate that is determined from the first voltage, a nominal read voltage and the target voltage.

Programming of memory cell having gate capacitively coupled to floating gate

A memory device with a memory cell and control circuitry. The memory cell includes source and drain regions formed in a semiconductor substrate, with a channel region extending there between. A floating gate is disposed over a first portion of the channel region for controlling its conductivity. A select gate is disposed over a second portion of the channel region for controlling its conductivity. A control gate is disposed over the floating gate. An erase gate is disposed over the source region and adjacent to the floating gate. The control circuitry is configured to perform a program operation by applying a negative voltage to the erase gate for causing electrons to tunnel from the erase gate to the floating gate, and perform an erase operation by applying a positive voltage to the erase gate for causing electrons to tunnel from the floating gate to the erase gate.

Method of programming a split-gate flash memory cell with erase gate

The disclosed embodiments comprise a flash memory device and a method of programming the device in a way that reduces degradation of the device compared to prior art methods.

System and method for programming split-gate, non-volatile memory cells

A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.

Non-volatile memory program algorithm device and method

A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, a control gate disposed over the floating gate, and an erase gate disposed over the first region. The method includes placing a small positive voltage on the unselected source lines, and/or a small negative voltage on the unselected word lines, during the read operation to suppress sub-threshold leakage and thereby improve read performance.

Low leakage, low threshold voltage, split-gate flash cell operation

A non-volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate.

Split gate non-volatile flash memory cell having a silicon-metal floating gate and method of making same

A non-volatile memory including a substrate of a first conductivity type with first and second spaced apart regions formed therein of a second conductivity type with a channel region therebetween. A polysilicon metal gate word line is positioned over a first portion of the channel region and spaced apart therefrom by a high K dielectric layer. The metal portion of the word line is immediately adjacent to the high K dielectric layer. A polysilicon floating gate is immediately adjacent to and spaced apart from the word line, and positioned over and insulated from another portion of the channel region. A polysilicon coupling gate is positioned over and insulated from the floating gate. A polysilicon erase gate is positioned on another side of and insulated from the floating gate, positioned over and insulated from the second region, and immediately adjacent to but spaced apart from another side of the coupling gate.

Non-volatile memory cell having a high K dielectric and metal gate

A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

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San Jose, CA, United States of America

Alexander Kotov