Oracle International Corporation

Oracle America, Inc.

Alexander Korobkov

Wai Chung William Au

Wai Chung W Au

Amit Agarwal

Subramanian Venkateswaran

Qing He

Bogdan Tutuianu

Michael Yu

Alexandre Ardelea

A method for modeling electrostatic discharges. The method may include obtaining a circuit netlist for an integrated circuit. The circuit netlist may describe connection information for various electronic components within the integrated circuit. The method may further include obtaining, by removing a portion of the electronic components from the circuit netlist, a reduced netlist. The method may further include determining, using the reduced netlist, various circuit parameters regarding an electrostatic discharge event for the integrated circuit. The method may further include simulating, using the circuit parameters, a discharge path within the integrated circuit for the electrostatic discharge event.

Iteratively simulating electrostatic discharges for a reduced netlist

A system that visualizes a clock tree for an integrated circuit receives an extracted cell library, an extracted clock netlist including clock headers and interconnects, and simulation results. The system generates an internal data structure for the clock headers, and divides the clock headers into a plurality of levels based on the interconnects. The system then orders the clock headers from a lowest level to a highest level, and displays the ordered clock headers in an untangled manner.

Integrated circuit clock tree visualizer

A system that simulates an integrated circuit is formed of a plurality of devices. The system initially performs a fundamental circuit simulation run using original parameters for the plurality of devices and an initial time step. The system generates one or more fundamental time steps from the fundamental circuit simulation run. The fundamental time steps are generated when changes that indicate state time derivatives during two or more successive integration steps are within a predetermined range. The system stores the one or more fundamental time steps as fundamental circuit events in an events queue, and updates the parameters for the plurality of devices based on the fundamental circuit events to generate one or more derivative circuits. The system then performs one or more derivative circuit simulation runs using the derivative circuits.

Integrated circuit simulation using fundamental and derivative circuit runs

An integrated circuit clock analysis system receives a cell library of gates of the integrated circuit and generates a macro model for each of the gates, where each macro model includes at least one of a nonlinear current source model, an input parasitics model or a nonlinear capacitors model. The system then tunes the macro models and generates a simulation deck from an electrical netlist of a layout of the integrated circuit and the tuned macro models. The system then performs clock analysis simulation based on the simulation deck.

Integrated circuit clock analysis with macro models

Embodiments of the invention provide systems and methods for parallelizing simulation of circuit partitions. A circuit is divided into a number of partitions, for example, according to channel-connected regions. In some embodiments, the partitions are sequenced and assigned to multiple threads for parallel analysis. Iterative timing analysis (ITA), or some other form of analysis, is performed on the partitions over a series of integration time steps. Using the multiple threads, some partitions are solved at later integration time steps while the ITA continues toward relaxation convergence for a current integration time step.

Parallel circuit simulation with partitions

A method for evaluating a device during circuit simulation includes receiving a first request including a first input value; and mapping the first input value to a first space in a table. The table is configured to store one or more table entries. A table entry includes an input value and a stored value. The stored value is obtained as a function of the input value from an analytical device model used to characterize the device during circuit simulation. The method includes determining whether the first space in the table is occupied by a first table entry; selecting a second table entry and a third table entry from the table when the first space in the table is not occupied by the first table entry, wherein the second table entry and the third table entry are neighbors in relation to the first space in the table; determining whether an accuracy criteria for performing a linear interpolation is satisfied as a function of the first input value, a stored value for the second table entry, and a stored value for the third table entry; and obtaining a first response value by performing the linear interpolation of the stored value for the second table entry and the stored value for the third table entry when the accuracy criteria is satisfied; and sending a response to the first request including the first response value. The first response value corresponds with the performance of the device when the device is configured using the first input value.

Method and system for evaluating a device during circuit simulation

A method for a power grid configured to supply current to a plurality of elements of a circuit. The method includes representing the power grid as a graph including a plurality of nodes and a plurality of edges, wherein each node of a portion of the plurality of nodes corresponds to an element of the plurality of elements each modeled as a current source, determining a characteristic matrix A of the power grid, wherein transient behavior of the power grid is represented by a set of linear equations of A*v=i, wherein v is a nodal voltage vector representing nodal voltages of at least a portion of the plurality of nodes and i is a current source vector representing currents supplied to at least a portion of the plurality of elements, identifying first and second partitions of the power grid based on a predetermined criterion, identifying first and second current source subvectors of the current source vector according to the first and second partitions of the power grid, identifying a first shell of the first partition based on worst case nodal voltage sensitivity analysis with respect to the first current source subvector, identifying a second shell of the second partition based on worst case nodal voltage sensitivity analysis with respect to the second current source subvector, and generating an analysis result of transient behavior of the power grid by analyzing, concurrently and independently, the first and second shells of the first and second partitions of the power grid, respectively.

Parallel power grid analysis

A system and method of analyzing a power grid in an integrated circuit includes inputting a circuit design to a test bench, inputting a plurality of initial values for the circuit design in to the test bench, setting a current time t to 0 value for an initial time (t) of the operation of the circuit design, representing each capacitor in an RC circuit corresponding to the power grid circuit design by the each capacitor's respective time variant equivalent companion model, describing each one of the plurality of RC equivalent circuits mathematically as one of a corresponding plurality of linear equations, storing the plurality of linear equations in a matrix Yfor time t, resolving the matrix Yto determine a DC operating point, updating the RC equivalent circuits and the corresponding plurality of linear equations at a second time step t=t+h where h is a time step value equal to the current time t and a next simulated operation time, storing the updated plurality of linear equations in a matrix Yfor time t, inverting the matrix Yto form inverted matrix Y, resolving the inverted matrix Y, calculating a new time step and setting the current time t to t+h, comparing the new time step h to a plurality of time steps in a time step database, selecting one of the plurality of time steps substantially equal to the new time step and recalling a solution corresponding to the selected time step.

System, method and apparatus for sensitivity based fast power grid simulation with variable time step

Techniques are provided for fast reduction of a system model, such as fast parasitics reduction of an electrical design. Delta loops, which comprise three nodes connected by three edges, may be identified. The netlist can be annotated with the number of delta loops to which an edge belongs and a delta loop identifier. Delta loops that share an edge may be assigned the same identifier. Identifying delta loops may be based on the intersection of binary search trees that are based on the netlist. In one embodiment, a cost of removing a node from the netlist is determined. Based on the annotations to the edges connected to a node under consideration for removal, the total number of delta loops that are shared by pairs of edges is determined. Based, at least in part, on the total number of common delta loops, a cost is determined of removing the node.

Fast reduction of system models

This invention provides techniques and tools for reducing circuit simulation time when an electronic circuit with multiple input vectors is simulated. Instead of running the simulation for each input vector one at a time, the circuit-simulation application runs the simulation of the circuit for all input vectors simultaneously. Efficiencies in the simulation are obtained during each iteration of a transient analysis by grouping circuit instances with different input vectors based on a predetermined criteria, and producing a combined solution for circuit instances within each group.

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San Jose, CA, United States of America

Alexander Korobkov