Analogic Corporation

Other

Alexander Kolchinsky

Hans J Weedon

Enrico Dolazza

Jeremy L Muller

Richard McMorrow

A virtual processor has a reconfigurable, programmable logic matrix array for processing data in accord with a hardware encoded algorithm, a memory for storing a plurality of hardware configuration files for the programmable logic matrix array, each configuration file for programming an algorithm to be executed by the matrix array, an input/output bus for supplying data to the matrix array for processing and for obtaining processed data from the matrix array, a memory device for storing data, a VPM controller for controlling the overall operation of the virtual processor including providing operation sequence maps, providing parameters for specific operations, and providing status information, a data bus controller for controlling the data flow to the matrix array for processing, and a configuration controller for controlling the sequence of reconfiguration of the matrix array to process data by a specific sequence of algorithms.

Virtual processor module including a reconfigurable programmable matrix

A reconfigurable sequential processor includes a data bank for storing data to be processed; a programmable logic block address generator for addressing data in the data bank; a programmable logic block arithmetic unit responsive to the data bank for processing the data addressed by the programmable logic block address generator; an address generator hardware configuration file having a plurality of configuration files for configuring the programmable logic block address generator in one of a plurality of addressing configurations in response to an address operational code; an arithmetic hardware configuration file having a plurality of configuration files for configuring the programmable logic block arithmetic unit in one of a plurality of processing configurations in response to an arithmetic operational code; and for delivering a series of operational codes to each configuration file for enabling the programmable logic block address generator and the programmable logic block arithmetic unit to be configured to perform sequentially a corresponding series of arithmetic logic operations on the data in the data bank.

Multibus sequential processor to perform in parallel a plurality of

A signal digitization system and method is disclosed which identifies a plurality of sets of spaced intervals of information; defines a strobing window within each spaced interval in one of the sets at a time; strobes the signal during the strobing window; integrates and holds the strobed signal; and digitizes the integrated signal.

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Andover, MA, United States of America

Alexander Kolchinsky