Intel Corporation

Apple Inc.

Alexander Klinkan

Stephan Henzler

Christoph Angerer

Franz Kuttner

Peter Preyler

Jochen Schrattenecker

Christoph Hepp

Andreas Langer

Jovan Markovic

Tobias Buckel

Damir Hamidovic

Eugen Pfann

Peter Plechinger

Nicholas Preyss

Wireless circuitry can include a processor that generates a baseband signal, an upconversion circuit that upconverts the baseband signals to a radio-frequency signal, and an amplifier that amplifies the radio-frequency signal. A tunable delay circuit can be used to selectively delay generation of the radio-frequency signal or to delay generation of another signal intended for the radio-frequency amplifier. The tunable delay circuit can be controlled using a closed-loop delay adaptation scheme. A feedback receiver that is coupled to an output of the amplifier can be used to generate a demodulated signal. A delay error measurement circuit can be used to receive the demodulated signal, to detect a peak by monitoring when an envelope of the demodulated signal crosses a threshold level, to compute an amount of asymmetry in the detected peak, and to output a signal that is used to control the tunable delay circuit.

Wireless circuitry with delay measurement and tuning

A radio-frequency amplifier can have a radio-frequency input configured to receive a radio-frequency signal and a control input for receiving a control signal. The radio-frequency signal can be generated using a first group of digital-to-analog converters (DACs), whereas the control signal can be generated using a second set of DACs. Data intended for the first group of DACs can be fed through a first set of retiming circuits and a first crossbar circuit. Data intended for the second group of DACs can be fed through a second set of retiming circuits and a second crossbar circuit. A low skew clocking interface and constant latency control and clock domain cross circuits can be employed to ensure that data streams arriving at the first group of DACs are time aligned with data streams arriving at the second group of DACs.

Wireless circuitry with time aligned data streams

An apparatus for interpolation of polar signals in RF transmitters is disclosed. The apparatus comprises an estimation circuit configured to receive an input in-phase (I) quadrature (Q) signal comprising a plurality of input IQ samples having a first sampling rate associated therewith, and determine a selection metric value indicative of a position of an IQ trajectory associated with one or more input IQ samples of the input IQ signal. The apparatus further comprises a selection circuit configured to receive the input IQ signal and the selection metric value; and adaptively provide the input IQ signal to a first interpolation circuit that implements a first interpolation method or to a second interpolation circuit that implements a second, different interpolation method, for generating interpolated polar samples at a second, different sampling rate, from the input IQ signal, based on the selection metric value.

Interpolation method for polar signals in radio frequency transmitters

Techniques are disclosed to provide a data dependent delay for a multi-phase transmitter architectures. These techniques include identifying a current segment occupied by a symbol associated with in-phase (I) and quadrature phase (Q) data within a data constellation based upon the number of phases used. Once the segment is identified, vector components are calculated as a function of the segment used to re-map the symbol within the constellation defined in accordance with the number of phases. The data delay may be performed in the baseband or at the RF rate to time-align local oscillator clocks with the delayed data, which is represented as the calculated vector components, for transmission. Further modifications to the RF-DAC operation to facilitate operation with the multi-phase system are also disclosed.

Multiphase transmitter digital front end

A communication system using adaptive sample rate reduction (ASRR) is disclosed. The system includes a digital front end (DFE) and a radio frequency (RF) interface. The DFE is configured to receive a baseband signal, identify reduced performance parameters for the baseband signal, reduce a sampling rate for the baseband signal based on the reduced performance parameters and generate a digital interface signal using the reduced sampling rate. The RF interface is configured to generate an analog TX signal from the digital interface signal.

Adaptive sample rate reduction for digital IQ transmitters

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Linz, Austria

Alexander Klinkan