Taiwan Semiconductor Manufacturing Comp. Ltd.

National Semiconductor Corporation

Intersil Americas Inc.

Maxim Integrated Products, Inc.

Stmicroelectronics Gmbh

Sgs-thomson Microelectronics Limited

Apple Inc.

Upek, Inc.

Alexander Kalnitsky

Albert M Bergemont

Kong-Beng Thei

Hsiao-Chin Tuan

Chien-Chih Chou

Yi-Huan Chen

Pavel Poplevine

Dun-Nian Yaung

Michael D Church

Shih-Fen Huang

Jhy-Jyi Sze

Chun-Ren Cheng

Felix Ying-Kit Tsui

Fu-Jier Fan

Harry-Hak-Lay Chuang

Chun-Wen Cheng

Chia-Hua Chu

Yimin Huang

Chung-Shi Liu

Jen-Cheng Liu

Alan H Kramer

Chin-Yu Ku

Chia-Shiung Tsai

Wei Cheng Wu

Ming Chyi Liu

Chun Lin Tsai

Kuo-Ming Wu

Kuo-Chio Liu

Chen-Hua Douglas Yu

Hsing-Chih Lin

Yi-Shao Liu

Tien-Wei Chiang

Hau-Yan Lu

Ching-Hua Hsieh

Yuichiro Yamashita

Chen-Jong Wang

Alan S Roth

Fu-Wei Yao

Ru-Liang Lee

Jen-Chou Tseng

Ru-Yi Su

Chih-Ping Chao

Chia-Wei Hsu

Ming-Fu Tsai

Hung-Jui Kuo

Yeur-Luen Tu

Mirng-Ji Lii

Wei-Cheng Wu

Ming-Che Ho

Eric Soenen

Yi-Wen Wu

Yu-Hung Cheng

Shawn Searles

Hung Cho Wang

Sheng-Huang Huang

Chung-Yi Yu

Fu-Lung Hsueh

Giovanni Gozzini

Cheng-Ta Wu

Ping-Yin Liu

Sheng-Chau Chen

Kuei-Sung Chang

Wen-De Wang

Hsin-Hung Chen

Chen-Yi Lee

Chi-Yuan Shih

Yi-Hsien Chang

Hung-Hua Lin

Yu-Chang Jong

Chih-Wen Hsiung

Szu-Yu Wang

Yi-Chuan Teng

Li-Feng Teng

Chen-Hao Chiang

Der-Chyang Yeh

Wen-Ting Chu

Kuo-Chi Tu

Ching-Wen Hsiao

Frank R Bryant

Yao-Wen Chang

Jui-Cheng Huang

Hsun-Chung Kuang

Chi-Ming Chen

Sheng-Hung Shih

Sheng-Chan Li

Hon-Lin Huang

Tung-Tsun Chen

Wen-Chuan Tai

Tzu-Jui Wang

Tzu-Yu Chen

Fusen E Chen

Shih-Pei Chou

Fei-Lung Lai

Hsiang-Fu Chen

Jiou-Kang Lee

Fu-Chen Chang

Larry Lingjer Wang

Hsin-Ting Huang

Chen-Liang Chu

Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC is manufactured by forming a plurality of deep trenches including an isolation trench and a logic device trench from a top surface of a substrate, filling an isolation material in the isolation trench and the logic device trench, removing the isolation material from the logic device trench, forming a first logic device by filling a first logic gate dielectric and a first logic gate electrode in the logic device trench, and forming first and second source/drain regions in the substrate on opposite sides of the logic device trench. The isolation material is kept in the isolation trench to form an isolation structure.

Trench gate high voltage transistor for embedded memory

Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) DoP image sensor and a method for forming the SOI DoP image sensor. In some embodiments, a semiconductor substrate comprises a floating node and a collector region. A photodetector is in the semiconductor substrate and is defined in part by a collector region. A transfer transistor is over the semiconductor substrate. The collector region and the floating node respectively define source/drain regions of the transfer transistor. A semiconductor mesa is over and spaced from the semiconductor substrate. A readout transistor is on and partially defined by the semiconductor mesa. The semiconductor mesa is between the readout transistor and the semiconductor substrate. A via extends from the floating node to a gate electrode of the readout transistor.

Device over photodetector pixel sensor

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a stack of gate layers over a substrate. The stack of gate layers includes a first dielectric layer on the substrate, a conductive layer on the first dielectric layer, and a polysilicon layer on the conductive layer. A pair of source/drain regions is formed on opposing sides of a central region of the polysilicon layer. The central portion of the polysilicon layer is converted to a first silicide layer. The first silicide layer is spaced between inner sidewalls of the polysilicon layer.

FUSI gated device formation

Voltage reference circuits are provided. A voltage reference circuit includes a transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit, and an output note. A gate and a drain of the flipped-gate transistor are coupled to a gate and a drain of the transistor. A bulk and a source of the flipped-gate transistor are coupled to a ground. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and a mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the first transistor in response to the mirroring current. The output node is coupled to a source of the transistor and the second current mirror unit, and configured to output a reference voltage. Size of the flipped-gate transistor is less than that of the first transistor.

Voltage reference circuit and method for providing reference voltage

In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

Recessed gate for an MV device

A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate having an isolation ring extending in the direction substantially parallel to the surface of the substrate, an active region over the substrate and laterally enclosed by the isolation ring, a seal ring structure over the substrate, the seal ring structure laterally enclosing the active region and including at least a wiring layer and at least a via layer, and an encapsulant material laterally enclosing the seal ring structure.

Semiconductor structure and manufacturing method of the same

The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Boundary design for high-voltage integration on HKMG technology

A semiconductor device includes a substrate, an isolation structure, a conductive structure, and a first contact structure. The isolation structure is disposed in the substrate. The conductive structure is disposed on the isolation structure. The conductive structure extends upwards from the isolation structure, in which the first contact structure has a top portion on the conductive structure and a bottom portion in contact with the isolation structure.

Electrical fuse (e-fuse) one-time programmable (OTP) device and manufacturing method thereof

A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.

Semiconductor device having metal gate and poly gate

In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.

Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices

A semiconductor structure includes a substrate and a dielectric material disposed over the substrate. A void is disposed within the dielectric material. A dielectric liner is disposed along inner sidewalls of the dielectric material proximate to the void. An inner surface of the dielectric liner defines an outer extent of the void, and the dielectric liner includes an inner liner layer and an outer liner layer.

Semiconductor structure and manufacturing method thereof

In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

Thicker corner of a gate dielectric structure around a recessed gate electrode for an MV device

Various embodiments of the present disclosure are directed towards an integrated chip including a capacitor over a substrate. The capacitor includes a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers and dielectric layers define a base structure and a first protrusion structure extending downward from the base structure towards a bottom surface of the substrate. The first protrusion structure comprises one or more surfaces defining a first cavity. A top of the first cavity is disposed below the base structure.

Trench capacitor profile to decrease substrate warpage

A method includes: receiving a composite substrate including a first region and a second region, the composite substrate comprising a semiconductor substrate and an insulator layer over the semiconductor substrate; bonding a silicon layer to the composite substrate; depositing a capping layer over the silicon layer; forming a trench through the capping layer, the silicon layer and the insulator layer, the trench exposing a surface of the semiconductor substrate in the first region; growing an initial epitaxial layer in the trench; removing the capping layer to form an epitaxial layer from the silicon layer and the initial epitaxial layer; forming a transistor layer over the epitaxial layer, the transistor layer including a first transistor and a second transistor in the first region and the second region, respectively; and forming an interconnect layer over the transistor layer and electrically coupling the first transistor to the second transistor.

The present disclosure relates to an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

Multi-function substrate

Growing community of inventors

San Francisco, CA, United States of America

Alexander Kalnitsky