International Business Machines Corporation

Alexander K Spencer

Robert L Mansfield

Joe C St Clair

Marc Segre

Leon Lumelsky

Barry Duane Williamson

Roger Ned Bailey

Christopher McCall Durham

Paul Gerard Villarrubia

Stephen Thomas Quay

David Scott Ray

Sharad Mehrotra

Carol Ivash Gabele

Parsotam Trikam Patel

Satish Gupta

James D Wagoner

Hector G Romero, Jr

Adjacent signal lines within the critical path of logic within an integrated circuit are checked for capacitive coupling induced signal delay variations resulting from concurrent signal transitions. When found, signal transition overlap is eliminated by delaying the clock edge (rising or falling) triggering the signal driving logic, without necessarily delaying the other clock edge. A delay circuit is incorporated into clock stages for the signal driving logic, and may be selectively actuated to delay the clock edge to particular signal driving logic circuits. Selection of signal lines in which signal transitions are to be delayed may be performed after manufacture of the integrated circuit, and iterative determinations may be required since signal adjustment may create new critical paths within the integrated circuit logic. Once the final signal adjustment configuration is determined, that configuration may be stored as a vector within a memory in the integrated circuit and read during power-up into a scan chain controlling the individual delay circuits.

Post-manufacture signal delay adjustment to solve noise-induced delay variations

A method for analyzing a design or a model of a microprocessor chip model is provided. A base chip model is generated, and it is modified with wire-only changes to produce a modified chip model. The modified chip model is compared to the base chip model to discern the wire-only changes to form a delta chip model. A set of values for RC delays and net capacitance based on the delta chip model is produced, and the modified chip model is timed using the set of values for RC delays and net capacitance on the delta chip model and RC delays and net capacitance on the base chip model.

Method and system for analyzing wire-only changes to a microprocessor design using delta model

A method and system for performing timing analysis on an integrated circuit design are disclosed. It is always advantageous to be able to conveniently perform a timing analysis on the entire IC design at any stage of the design process in order to gain more accurate timing information about the design. However, at an early stage of the design process, the available physical circuit data are often incomplete, not to mention these preliminary data are usually of a lower quality as far as capability of providing an accurate RC delay and capacitance estimation is concerned. To make the best usage of the preliminary data, the present disclosure describes a method of performing a fleeting timing analysis that can be very useful during an early floor planning stage of the design process when there is no opportunity to buffer or widen any exceptionally long interconnect wires within the IC circuit design. As a result, much faster design turn-around time may be achieved because buffer insertion need not be run for every new pass of the physical circuit design data.

Method and system for performing timing analysis on an integrated circuit design

An apparatus and method provides additional logic in both execution units of a dual execution unit processing in order to determine if the instruction is interruptable. Additionally, backout logic is provided for saving the contents of unique registers. The backout logic uses two decodes to determine if the instruction currently executing modifies the unique registers. It is possible for a single instruction to modify more than one unique register. The backout logic of the present invention resides in both of the execution units and particularly in the unit which contains the unique register being modified by the executing instruction. If an instruction is being executed which modifies one of the unique registers, then the contents of that register are saved in a backout latch. A cancel signal is then provided if the interruptable instruction executes without causing an interrupt. However, if the interruptable instruction does cause an interrupt, then the contents of the backout latch are reloaded into the execution units.

System and method for saving state information in a multi-execution unit

A technique for use in an I/O channel to increase bus bandwidth during DMA data transfers between main system memory and a communication link is disclosed, including a pair of buffers, a plurality of counters adapted to selectively contain a count of data increments therein, and enhanced DMA control logic for monitoring buffer data content amount, and at a predetermined time during a given transfer initiating a bus arbitration so that it is completed simultaneously with the given transfer, thereby enabling the next data transfer from the buffer in use to immediately commence.

Look ahead bus transfer request

A timer including a counter circuit that continuously provides an output of an iteratively increasing sequence of bits. The timer includes a timeout data circuit that forms a timeout data word from a specified time period and a first counter circuit output. A register is provided that stores the timeout data word at an address formed from a second counter circuit output. A comparison circuit is provided that compares each counter output with a timeout data word at the address formed from that counter output and provides a timeout signal when they are equal. This timer includes a constantly incrementing counter to address a register that includes a multiple of timeout condition specifications, and as a determination of when the timeout conditions stored in the register occur.

Multiple event timer circuit

A processing system is provided that includes an external device connected to a processor. The external device has the capability of responding to external device commands wherein each of these external device commands is performed within at least one fixed time cycle. The processor provides these external device commands and, further, includes the means for executing instructions that not only specify the external device commands but also specify at least one internal command to be performed by the processor simultaneously with the performance of the external device command and within the same fixed time cycle. In the disclosed embodiment, a graphics display system is provided that includes a system processor, a graphic processor, a graphics memory and a display device. The graphics processor receives instructions from the system processor which specifies commands to be executed by both the graphics processor and the graphics memory. Each graphics memory command is executed within a fixed time cycle simultaneously with the execution of a corresponding graphics processor command executed within the graphics processor.

Graphics function controller for a high performance video display system

A display adapter for displaying graphics data in pixel form on a high resolution display monitor includes a digital signal processor for managing adapter resources and controlling coordinate transformations, a system storage which is divided into a first portion for storing instructions for the digital signal processor and the second portion for storing data representing information to be displayed, an input buffer for permitting asynchronous and overlapped communication between the graphics display adapter and a host computer to speed operation of the system, a pixel processor for drawing vectors and manipulating areas to be displayed on the monitor, a bit mapped frame buffer, a color palette connected to outputs of the frame buffer for providing appropriate color signals to the high resolution monitor and a cursor circuit for controlling display of a cursor on the screen on the monitor.

High resolution graphics display adapter

In a graphics display system a counter for performing either a line drawing algorithm or a bit block transfer algorithm where the counter is performing the bit block transfer algorithm includes a first counter circuit counting from a first initial state to a first predetermined value and a second counter circuit counting from a second initial state to a second predetermined value. The second counter counts in response to the first counter reacing to its predetermined value. In support of a line drawing algorithm, the counter circuit reconfigures itself to provide a first counter to count from its first initial state to the first predetermined value and a second counter to compute a parameter value and to conditionally count from a second initial value to a second predetermined value in response to the value of this parameter. These counters are connected to an addressing circuit to increment the addresses in performance of the algorithms. This counter circuit capability increases the speed at which line draw functions and bit block transfer functions can be accomplished in a graphics display system processor.

Graphics display system function circuit

A multichannel data path architecture which assists a host processor in communication with the frame buffer in order to increase the overall system performance. The architecture provides automatic frame buffer data path rearrangement depending on the pixel address and the host data interpretation. It utilizes a minimum of shift registers, accumulators and control circuitry to provide the requisite storage, reconfiguration and frame buffer access functions. The architecture extends bit-blt (bit block transfer) conventional operations in order to provide high quality 'antialiased' text and graphics directly in the architecture without requiring the calculation of colors by the host processor. Finally, it assists the 'burst' mode update of an arbitrary single plane of a frame buffer, which is especially important when high denisty chips are used for the frame buffer implemenation.

Pixel data path for high performance raster displays with

A graphics display system including a circuit that receives graphics information to be displayed and a memory that stores the graphics information in a memory array that includes a portion that directly corresponds to the image area for display. The memory provides a single access operation to the array during a single memory cycle. Circuitry is provided that is connected to the receiving means and to the memory that provides graphics information to an N by M portion of the memory array during a single memory cycle (wherein N and M are integers each greater than one). A display is connected to the memory that displays the graphics information contained in the image area array portion of the memory. The graphics display system further includes the capability to provide a patterned line intersection where the continuity of the line pattern is maintained along the intersection of the lines.

Growing community of inventors

Austin, TX, United States of America

Alexander K Spencer