Apple Inc.

Alexander K Kan

Richard Warren Schreyer

Michael Imbrogno

Gokhan Avkarogullari

Terence M Potter

James J Ding

Kenneth Christian Dyke

Michal Valient

Sean P James

Jenny Hu

Yingying Tang

James R Montgomerie

Mehmet N Agaoglu

Kelvin C Chiu

Chaohao Wang

Andrey Pokrovskiy

Wanqing Xin

Eric O Sunalp

Yuhui Li

An electronic device may include a display. Control circuitry may operate the display at different frame rates such as 60 Hz, 80 Hz, and 120 Hz. The control circuitry may determine which frame rate to use based on a speed of animation on the display and based on a type of animation on the display. To mitigate the appearance of judder as the display frame rate changes, the control circuitry may implement techniques such as hysteresis (e.g., windows of tolerance around speed thresholds to ensure that the display frame rate does not change too frequently as a result of noise), speed thresholds that are based on a user perception study, consistent latency between touch input detection and corresponding display output across different frame rates (e.g., using a fixed touch scan rate that is independent of frame duration), and animation-specific speed thresholds for triggering frame rate changes.

Displays with variable frame rates

Techniques are disclosed relating to specifying memory consistency constraints. In some embodiments, an instruction may specify, for a memory operation, a type of memory consistency and a scope at which to enforce the type of consistency. For example, these fields may specify whether to sequence memory accesses relative to the operation at one or more of multiple different cache levels based on the type of memory consistency and the scope.

Memory consistency in memory hierarchy with relaxed ordering

The disclosure pertains to techniques for operation of graphics systems and task execution on a graphics processor. One such technique comprises a computer-implemented method for task execution on a graphics processor, the method comprising creating a data structure for grouping data resources, populating the data structure with two or more data resources for encoding into a graphics processing language by an encoding object, passing the data structure to a first programming interface command, the first programming interface command configured to access the data structure's data resources, triggering execution of a first function on a graphics processer in response to passing the data structure to the first programming interface command, passing the data structure to a second programming interface command, the second programming interface command configured to access the data structure's data resources, and triggering execution of a second function on the graphics processer in response to passing the data structure to the second programming interface command.

Task execution on a graphics processor using indirect argument buffers

Systems, computer readable media, and methods for a unified programming interface and language are disclosed. In one embodiment, the unified programming interface and language assists program developers write multi-threaded programs that can perform both graphics and data-parallel compute processing on GPUs. The same GPU programming language model can be used to describe both graphics shaders and compute kernels, and the same data structures and resources may be used for both graphics and compute operations. Developers can use multithreading efficiently to create and submit command buffers in parallel.

System and method for unified application programming interface and model

Techniques are disclosed relating to synchronizing access to pixel resources. Examples of pixel resources include color attachments, a stencil buffer, and a depth buffer. In some embodiments, hardware registers are used to track status of assigned pixel resources and pixel wait and pixel release instruction are used to synchronize access to the pixel resources. In some embodiments, other accesses to the pixel resources may occur out of program order. Relative to tracking and ordering pass groups, this weak ordering and explicit synchronization may improve performance and reduce power consumption. Disclosed techniques may also facilitate coordination between fragment rendering threads and auxiliary mid-render compute tasks.

Resource synchronization for graphics processing

The disclosure pertains to techniques for operation of graphics systems and task execution on a graphics processor. One such technique comprises a computer-implemented method for task execution on a graphics processor, the method comprising creating a data structure for grouping data resources, populating the data structure with two or more data resources for encoding into a graphics processing language by an encoding object, passing the data structure to a first programming interface command, the first programming interface command configured to access the data structure's data resources, triggering execution of a first function on a graphics processor in response to passing the data structure to the first programming interface command, passing the data structure to a second programming interface command, the second programming interface command configured to access the data structure's data resources, and triggering execution of a second function on the graphics processor in response to passing the data structure to the second programming interface command.

Methods, systems and devices are disclosed to examine developer supplied graphics code and attributes at run-time. The graphics code designed for execution on a graphics processing unit (GPU) utilizing a coding language such as OpenCL or OpenGL which provides for run-time analysis by a driver, code generator, and compiler. Developer supplied code and attributes can be analyzed and altered based on the execution capabilities and performance criteria of a GPU on which the code is about to be executed. In general, reducing the number of developer defined work items or work groups can reduce the initialization cost of the GPU with respect to the work to be performed and result in an overall optimization of the machine code. Manipulation code can be added to adjust the supplied code in a manner similar to unrolling a loop to improve execution performance.

Combining compute tasks for a graphics processing unit

An image may be divided into tiles, each tile including a multitude of pixels. For each tile, a list of primitive groups that intersect the tile and an initial list of volumes that intersect the tile may be generated. For each primitive group in the list of primitive groups, a per-primitive group list of volumes may be generated. The per-primitive-group list of volumes may include volumes from the initial list of volumes whose depth range overlaps with a depth range of the primitive group. Pixels in the tile which intersect the primitive group may be shaded using the per-primitive-group list of volumes.

Growing community of inventors

San Francisco, CA, United States of America

Alexander K Kan