Cirrus Logic Inc.

Genesis Microchip Corporation

Paradise Electronics, Inc.

Genesis Microchip (delaware) Inc.

Nvidia Corporation

S3 Incorporated, Inc.

Nvidia International, Inc.

Tamiras Per Pte. Ltd., LLC

Alexander Julian Eglit

Vlad Bril

Robin Sungsoo Han

Sridhar Kotha

Rakesh Kumar Bindlish

Tzoyao Chan

John Lattanzi

Ken Fuiks

Sagar Waman Kenkare

Jim Zong

Muralidhar Reddy Jammula

Vald Bril

Robin Sungsop Han

A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.This invention is directed to a method of scaling a source image formed of a number of source image elements to provide a destination image formed of a number of destination image elements using a line buffer and no frame buffer.

Method and system for displaying an analog image by a digital display device

A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.Scaling a source image formed of a number of source image elements to provide a destination image formed of a number of destination image elements using a line buffer and no frame buffer.

An over-sampled sequence detector operates on sampled data and tracks the detection reliability of the sampled data. The detector separately analyzes sample sequences for different sampling phases and then picks a sample sequence that allows for the most reliable detection. For the different sampling phases, the detector inspects some amount of look-behind and look-ahead information in order to improve upon simple symbol-by-symbol detection. The over-sampled information is used to further improve detection performance.

Adaptive reception techniques for over-sampled receivers

A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.

Method and apparatus for asynchronous display of graphic images

Method and apparatus for reception of data over a transmission link

Method and apparatus for reception of data over digital transmission link

A monolithic integrated circuit for use in a digital display unit. The circuit may include an analog-to-digital converter (ADC), a scaler and a clock recovery circuit. The present invention enables the integration of at least these components into a single monolithic integrated circuit while maintaining reasonable display quality. Specifically, the monolithic integrated circuit is designed for substantial immunity from noise, which may otherwise result from integration.

Monolithic integrated circuit implemented in a digital display unit for generating digital data elements from an analog display signal received at high frequencies

A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform(DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.

A digital display unit adjusting the phase of a sampling clock based on the examination of a display data signal contained in a received analog display signal. The phase may be adjusted by determining a boundary between display data portions representing successive pixel data elements. As the boundaries provide the timing information related to the source clock, the phase of the sampling clock can be adjusted when ever the boundaries can be determined accurately. The phase of the sampling clock can be adjusted potentially every sampling clock cycle if the boundaries can be determined. The area for examination can be minimized by first determining an expected boundary based on synchronization signal accompanying the analog display data, and examining only a small area surrounding the expected boundary.

Digital display unit which adjusts the sampling phase dynamically for accurate recovery of pixel data encoded in an analog display signal

A receiver to recover data encoded at high speed in a signal over a serial communication channel. A static phase determination circuit indicates whether the signal is early, late or neutral relative to a sampling clock. The sampling clock is used to oversample the signal to generate multiple samples. A token analyzer examines the transitions around a current symbol to determine any short term phase shifts of the boundaries between symbols. The short term phase shifts and the static phase together may be used to accurately select the samples representing the symbols without requiring extensive processing.

Receiver to recover data encoded in a serial communication channel

A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.

Circuit and method for generating pixel data elements from analog image data and associated synchronization signals

A flat panel display controller is provided with a circuit for monitoring clocking signal(s) to the flat panel display. A clocking signal output to the flat panel display may be fed back to the display controller using a conventional I/O pad. In the preferred embodiment, the fed back clocking signal resets a counter. In a second embodiment, the fed back clocking signal may then pass through an edge detector whose output then resets the counter. The counter will overflow if a edge signal is not received within a predetermined time period. If an overflow occurs, the carry signal of the counter will initiate a flat panel power shutdown through power control circuitry. The clock signal for the counter may be derived from an off-chip oscillator such that if a failure occurs within the display controller, the counter will continue to function.

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Half Moon Bay, CA, United States of America

Alexander Julian Eglit