Applied Micro Circuits Corporation

Mmc Networks, Inc.

Other

Multimedia Communications, Inc.

Alexander Joffe

Asad Khamisy

Dmitry Vyshetsky

Ari Birger

Nathan Y Elnathan

Ilan Pardo

Oran Uzrad-Nali

Pravat Mishra

Eugene N Opsasnick

Simon H Milner

Logic (also called 'synchronizing logic') in a co-processor (that provides an interface to memory) receives a signal (called a 'declaration') from each of a number of tasks, based on an initial determination of one or more paths (also called &#x201c;code paths&#x201d;) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called &#x201c;disabled&#x201d; task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called &#x201c;needy&#x201d; tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).

Logic for synchronizing multiple tasks

In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.

Systems and methods for multi-tasking, resource sharing, and execution of computer instructions

Logic for synchronizing multiple tasks at multiple locations in an instruction stream

This disclosure relates to communications among processors, coprocessors and memory. Specifically, a method and apparatus provide a single-cycle instruction ('store-and-load') that stores a command to a co-processor to atomically process data and that loads resultant processed data.

Method and apparatus for issuing a command to store an instruction and load resultant data in a microcontroller

Tasks are dynamically allocated to process packets. In particular, packets of data to be processed are assigned a packet identification. The packet identification includes a lane and a packet sequence number. The term 'lane' as used herein refers to a port number and a direction (i.e. ingress or egress), such as Port 3 Egress. A set of resources (e.g., registers and memory buffers) are associated with each lane. The task is allowed to access resources associated with the lane. In some embodiments, a task may change the port that it services and use the resources associated with that port.

Dynamic allocation of packets to tasks

In a computer system including at least one microcontroller, by suspending tasks after execution of particular instructions, such as a load-register-from-external-memory instruction, or when a resource is not ready, unnecessary attempts to execute subsequent instruction can be avoided. If a processor register has not yet been loaded and the next instruction attempts to use that register, the task will suspend. A task can also be suspended by incorporating a computer instruction that suspends the task after execution. A task can also be suspended by utilizing resources that provide one or more suspend indications. Such suspend indications can include a 'suspend-and-resume-on-current-instruction' indication that suspends the current task and leaves the program counter (PC) value pointing to the current instruction or can include a 'suspend-and-resume-on-next-instruction' indication that suspends the current task after completion of the current instruction and advances the program counter (PC) value to point to the next instruction. When the task becomes active again, the task begins execution at the instruction pointed to by the PC.

Method and apparatus to suspend and resume on next instruction for a microcontroller

Systems and methods for multi-tasking, resource sharing and execution of computer instructions

Logic (also called 're-ordering semaphore') issues semaphore grants to access a shared resource in an order different from the order in which semaphore requests for accessing the shared resource are received. The re-ordering semaphore needs to receive a semaphore release between any two semaphore grants. There is no limit on the duration between a semaphore grant and a semaphore release, so that a task that receives a semaphore grant can use the shared resource for any length of time. In one embodiment, each request is associated with a number indicative of the order in which grants are to be issued, and the re-ordering semaphore uses this number in deciding which request is to be granted. The number can be a sequence number that is indicative of the order of arrival of packets that generated the requests.

Shared resource access via declarations that contain a sequence number of a packet

A co-processor (also called 'memory co-processor') provides an interface to a memory, by executing instructions on data held in the memory. The co-processor uses a specified address to fetch data from memory, performs a specified instruction (such as incrementing a counter or policing) on the data to obtain modified data, and writes the modified data back to memory at the same address. Depending on the embodiment, the memory co-processor may include a first buffer for holding instructions that may be received back to back, in successive clock cycles. Instead of or in addition to the first buffer, the memory co-processor may include a second buffer for holding data to be written to memory back to back, in successive clock cycles. In some embodiments, the memory co-processor also receives (and maintains in local storage) the identity of a task that generates the specified instruction, so that the same cask may be awakened after the instruction has been executed.

Memory co-processor for a multi-tasking system

Multiple attempts are made to identify an entry in a cache. For example, a first attempt uses a RAM-based addressing structure (such as the above-described table) and a second attempt (on failure of the first attempt) uses a CAM-based addressing structure. The RAM-based addressing structure is faster than the CAM based-addressing structure, and in cases of a hit on the first attempt, cache performance is based on RAM cycle time rather than CAM cycle time. On the other hand, a miss on the first attempt does not mean that the data is not present in the cache. Instead, a second attempt using the CAM in the traditional manner finds the data if present in the cache.

Context based cache indexing

Data flows are queued in an active queue ( ) waiting for transmission. In each time slot, one data flow can be dequeued from the head of the active queue, and a data unit can be transmitted on the data flow. Then the data flow is placed in a queue &ldquo;i&rdquo; which is one of the queues , . . . N. Data flows are transferred from queue &ldquo;i&rdquo; to the active queue once in every 2 time slots. When a data flow is dequeued from the active queue and transferred to queue i, the queue number &ldquo;i&rdquo; is determined as i&equals;log &Dgr;, rounded to an integer, where A is the number of time slots in which one data unit must be transmitted from the data flow in order to meet a data flow bandwidth parameter. If the data flow has waited for &ldquo;d&rdquo; time slots in the active queue before being dequeued, then i&equals;log (&Dgr;&minus;d), rounded to an integer.

Selection of data for network transmission

Different frames received on a first port are processed by different processing channels in parallel. The processed frames are transmitted to a second port in the same order in which they were received on the first port. The ordering is maintained using a FIFO that receives the number of a processing channel whenever a frame is dispatched to the processing channel. The processing channels are selected to provide frames to the second port in the order of the channel numbers in the ordering FIFO.

Growing community of inventors

Palo Alto, CA, United States of America

Alexander Joffe