International Business Machines Corporation

Alexander Joel Suess

Kerim Kalafala

Nathaniel Douglas Hieter

David James Hathaway

Shyam Ramji

Gregory M Schaeffer

Chandramouli Visweswariah

Stephen Gerard Shuma

Eric A Foreman

Jeffrey G Hemmett

Vladimir P Zolotov

Paul Gerard Villarrubia

Natesan Venkateswaran

Lakshmi Narasimha Reddy

Michael H Wood

Benjamin Neil Trombley

Frank Musante

Gi-Joon Nam

Myung-Chul Kim

Peter Claude Elmendorf

Arjen Alexander Mets

Cindy ShuiKing Washburn

Brent A Anderson

Albert Manhee Chu

David S Wolpert

Leon Jacob Sigal

Sharad Mehrotra

Adam P Matheny

Ying Zhou

Vasant B Rao

Sridhar H Rangarajan

Byron Lee Krauter

Basanth Jagannathan

Hemlata Gupta

Chandramouli V Kashyap

Harry John Beatty, Iii

James Charles Gregerson

Michael Kazda

Ofer Geva

Laura R Darden

George Antony

Mihir Choudhury

David John Geiger

Peihua Qi

Alex Rubin

Bijian Chen

Revanta Banerji

Douglas Keller

Chaitanya Ravindra Peddawad

William E Dougherty

Paul M Campbell

Jeffrey S Piaget

Josiah Hamilton

James Leland

Stephen G Shurma

To increase the efficiency of electronic design automation, at an end point of physical design synthesis optimization flow for a putative integrated circuit design having a plurality of nets, identify at least one congested region in the putative integrated circuit design. Identify those of the nets of the putative integrated circuit design traversing through the at least one congested region, to obtain a plurality of candidate nets for demotion. Demote a plurality of selected nets, selected from the plurality of candidate nets for demotion, from an upper routing layer of the putative integrated circuit design to a lower routing layer of the putative integrated circuit design. At least some of the plurality of selected nets experience a loss of timing quality of result after the demoting.

Routing layer re-optimization in physical synthesis

Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.

Region-based power grid generation through modification of an initial power grid based on timing analysis

A system and method to perform physical synthesis to transition a logic design to a physical layout of an integrated circuit include obtaining an initial netlist that indicates all components of the integrated circuit including memory elements and edges that interconnect the components. The method also includes generating a graph with at least one of the memory elements and the edges carrying one or more signals to the at least one of the memory elements or from the at least one of the memory elements. The components other than memory elements are not indicated individually on the graph. The netlist is updated based on the graph.

Memory element graph-based placement in integrated circuit design

A system to develop an integrated circuit includes a latch identifier module to identify a first child latch placed at a first location in a first child macro of a parent macro and a second child latch placed at a second location in a second child macro of the parent macro. The second child latch is located away from the first child latch. The system further includes a latch location optimization module and a latch placement module. The latch location optimization module determines a target timing parameter threshold and determines a first actual timing parameter. The latch placement module changes the first location of the first child latch and/or the second location of the second child latch to generate an optimized parent macro based on the changed locations. The latch location optimization module re-executes the latch optimization process to determine a second actual timing parameter based on the changed locations.

Out-of-context feedback hierarchical large block synthesis (HLBS) optimization

A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.

Leverage cycle stealing within optimization flows

To increase the efficiency of electronic design automation, in a putative electronic logic circuit design, at least one transparent latch is identified as a candidate for slack stealing. An initial timing slack, available for stealing, and associated with the at least one transparent latch, is determined. Responsive to a determination that the initial timing slack available for stealing is insufficient, it is determined whether the initial timing slack available for stealing is on a feedback path. If so, responsive to determining that the initial timing slack available for stealing is on the feedback path, the initial timing slack available for stealing is replaced with a next worse slack.

Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuits

Technical solutions are described herein for fabrication of a chip with optimized chip design during the logical synthesis phase of the fabrication. An example method includes optimizing, by a physical synthesis system, a chip design for a chip to be fabricated, the optimization performed according to a first performance metric for the entire chip. The method further includes receiving, by the physical synthesis system, a feedback input comprising a region of the chip and a second performance metric associated with the region. The method further includes modifying, by the physical synthesis system, the chip design by optimizing the region of the chip according to the second performance metric. The method further includes sending, by the physical synthesis system, the modified chip design for fabrication of the chip.

Automated region based optimization of chip manufacture

A computer-implemented method of cell placement is provided. The method includes representing a non-rectangular cell to be placed into a cell row and searching the cell row to identify existing objects that are representative of cells in the cell row that are disposable to share space with the non-rectangular cell. The method further includes determining whether a representation of the non-rectangular cell is fittable into a modified mapping of the existing objects in the cell row and, in an event the representation is fittable into the modified mapping, overlapping the representation over one or more of the portions of the existing objects.

Cell placement in a circuit with shared inputs and outputs

Systems and methods of performing boundary assertion-based power recovery in integrated circuit design set boundary assertions based on a specified slack value. A boundary defines a set of components of the integrated circuit and setting the boundary assertions includes specifying arrival times at input pins of the set of components and required arrival times at output pins of the set of components. The method includes performing timing analysis of the set of components and performing the power recovery by replacing ones of the set of components based on a result of the timing analysis. The integrated circuit design is provided for fabrication based on completing the power recovery.

Boundary assertion-based power recovery in integrated circuit design

Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.

Optimizing placement of circuit resources using a globally accessible placement memory

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Hopewell Junction, NY, United States of America

Alexander Joel Suess