Advanced Micro Devices Corporation

Ati Technologies Ulc

Globalfoundries Inc.

Alexander J Branover

Benjamin Tsien

Maurice B Steinman

Thomas James Gibney

John P Petry

Mihir Shaileshbhai Doctor

Christopher T Weaver

Indrani Paul

Stephen Victor Kosonocky

Vydhyanathan Kalyanasundharam

Chintan S Patel

Ashish Jain

Ming L So

John Kalamatianos

Jonathan Mercer Owen

Guhan Krishnan

Andrew William Lueck

Frank P Helms

Xiaojie He

William Lloyd Bircher

Sonu Arora

Sridhar Varadharajulu Gada

Samuel D Naffziger

Philip Ng

Kevin Michael Lepak

Ljubisa Bajic

Denis J Foley

Sebastien Nussbaum

Alan Dodson Smith

Norman M Hack

Elliot H Mednick

Paul Edward Kitchin

Francisco Leonel Duran

Oswin Hall

Denis Rystsov

Dennis Au

Jyoti Raheja

Krishna Sai Bernucho

Biao Zhou

Xiao Gang Zheng

Fei Fei

Evgeny Mintz

Felix Yat-Sum Ho

Greg Sadowski

James Raymond Magro

Anthony Asaro

Ganesh Balakrishnan

David A Kaplan

Christopher Jude Brennan

Ronald Perez

Carl Kittredge Wakeland

Marvin A Denman

Paul Blinzer

Steven Kommrusch

Oleksandr Khodorkovsky

Hui Zhou

Walter G Fry

Kostantinos Danny Christidis

Madhu Saravana Sibi Govindan

William Kurt Lewchuk

Stephen David Presant

William A Moyes

Bill K C Kwan

Ann M Ling

W Kurt Lewchuk

Pravesh Gupta

Chen-Ping Yang

Ali Ibrahim

James B Fry

Carl D Dietz

Paul Mackey

Michael J Tresidder

Andrej Kocev

Akshay Lahiry

Adam N C Clark

Gary H Simpson

Rostyslav Kyrychynskyi

Dilip Kumar Jha

Mom-Eng Ng

Douglas Richard Beard

Rajen S Ramchandani

Joyce C Wong

Edgar Munoz

MingLiang Lin

Joe J Sargunaraj

Felix Ho

Joseph Scanlon

Bradley Kent

Jose G Cruz

Nat Barbiero

Mahesh UdayKumar Wagh

Xiaogang Zheng

Dan P Shimizu

Laura M Smith

Hemant R Mohapatra

William K Lewchuk

William L Bircher

A method, system, and apparatus determines whether a task should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. The task is relocated from the first processor to the second processor and executed on the second processor based on the comparing.

Method of task transition between heterogenous processors

Runtime flushing to persistency in heterogenous systems is described. In accordance with the described techniques, a system may include a persistent memory in electronic communication with at least one cache and a controller configured to command the at least one cache to flush dirty data to the persistent memory in response to a dirtiness of the at least one cache reaching a cache dirtiness threshold.

Runtime flushing to persistency in heterogenous systems

The disclosed computer-implemented method includes detecting a low utilization time period for memory traffic between a cache and memory, selecting from the cache, in response to detecting the low utilization time period, a dirty cache entry based on one or more factors, and writing the dirty cache entry back to the memory during the low utilization time period. Various other methods, systems, and computer-readable media are also disclosed.

Dynamically controlled cache rinsing

An exemplary system comprises a cluster of nodes that are communicatively coupled to one another via at least one direct link and collectively include a plurality of memory devices. The exemplary system also comprises at least one system memory manager communicatively coupled to the cluster of nodes. In one example, the system memory manager is configured to allocate a plurality of sharable memory pools across the memory devices. Various other systems, methods, and computer-readable media are also disclosed.

Systems and methods for sharing memory across clusters of directly connected nodes

Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain that is powered off in the power management state. In some implementations, the power domain is powered off in the mode. In some implementations, the device is powered on in the mode via a power rail that is specific to the mode. In some implementations, the entry condition of the mode includes an amount of data stored for display in a display buffer falling below a threshold amount.

On-demand IP initialization within power states

Devices and methods for cache prefetching are provided. A device is provided which comprises a quality of service (QOS) component having first assigned registers used to store data to execute a program, a plurality of non-QOS components having second assigned registers used to store data to execute the program and a power management controller, in communication with the QOS component and the non-QOS components. The power management controller is configured to issue fences for the non-QOS components when it is determined that one or more of the non-QOS components are idle, issue a fence for the QOS component when the fences for the non-QOS components are completed and enter a reduced power state when the fences for the non-QOS components and the fence for the QOS component are completed.

Device and method for two-stage transitioning between reduced power states

A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.

Method and apparatus for managing power states

A data processor includes a plurality of requestors, a plurality of responders, and a data fabric. The data fabric is for routing requests between the plurality of requestors and the plurality of responders and has a plurality of non-operational power states including a normal C-state and a light-weight C-state. The light-weight C-state has lower entry and exit latencies than the normal C-state. The data fabric monitors traffic through the data fabric and places the data fabric in the light-weight C-state in response to detecting an idle traffic state.

Data fabric C-state management

A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.

Technique for extended idle duration for display to improve power consumption

A technique for operating a cache is disclosed. The technique includes utilizing a first portion of a cache in a directly accessed manner; and utilizing a second portion of the cache as a cache.

Technique to enable simultaneous use of on-die SRAM as cache and memory

A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response to receiving an acknowledgement from the component of a request from the power management controller to remove power to the component, and executes a process to exit the component from the reduced power state in response to the component being active.

Device and method for efficient transitioning to and from reduced power state

A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.

Allocation control for cache

A processing system that includes a shared data fabric resets a first client processor while operating a second client processor. The first client processor is instructed to stop making requests to one or more devices of the shared data fabric. Status communications are blocked between the first client processor and a memory controller, the second client processor, or both, such that the first client processor enters a temporary offline state. The first client processor is indicated as being non-coherent. Accordingly, when the processor is reset some errors and efficiency losses due messages sent during or prior to the reset are prevented.

Shared data fabric processing client reset system and method

Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.

Using a hardware-based controller for power state management

A method and apparatus for managing a controller includes indicating, by a processor of a first device, to the controller of a second device to enter a second power state from a first power state. The controller of the second device responds to the processor of the first device with a confirmation. The processor of the first device transmits a signal to the controller of the second device to enter the second power state. Upon receiving a wake event, the controller of the second device exits the second device from the second power state to the first power state.

Method and apparatus for managing a controller in a power down state

Growing community of inventors

Chestnut Hill, MA, United States of America

Alexander J Branover