Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

Nxp B.v.

Other

Alexander Hoefler

Gowrishankar L Chindalore

James David Burnett

Nihaar N Mahatme

Craig T Swift

Paul A Ingersoll

Scott Ives Remington

Brad John Garni

Marius K Orlowski

Frank Kelsey Baker, Jr

Ko-Min Chang

Hubert Martin Bode

Anis Mahmoud Jarrar

Erwin J Prinz

Colin MacDonald

Lawrence N Herr

Glenn Charles Abeln

Jeffrey William Waldrip

Chi Nan Brian Li

Ravindraraj Ramaraju

Hector Adrian Sanchez

Sinan Goktepeli

Prashant U Kenkare

Shayan Zhang

Thomas E Tkacik

Bruce L Morton

Jane A Yater

Srikanth Jagannathan

Mohamed S Moosa

Qadeer A Qureshi

Jose A Lyon

Savithri Sundareswaran

Rishi Bhooshan

Robert Arthur Jensen

Sayeed Ahmed Badrudduza

Matthew B Rutledge

Khoi Van Dinh

Der-Gao Lin

Chris P Nappi

Benjamin S Huang

John M Dalbey

Andrew H Payne

Jeffrey Stump

Shilpa Gupta

An integrated circuit (IC) for detecting single event latch-ups (SELs) includes a plurality of wells of a memory circuit and a detection circuit. The detection circuit includes a selection circuit, a comparison circuit, and a fault collection and control management circuit. The selection circuit selects a well of the plurality of wells to sense a voltage or a current in the selected well. The well is selected based on a select signal that indicates a location of the well. The comparison circuit compares the sensed voltage or current with a predetermined threshold to generate a fault signal that may be indicative of the SEL in the selected well. The SEL may be indicative of a fault in the memory circuit. The fault collection and control management circuit determines corrective actions based on the detection of the location of the SEL.

System and method for improving safety of integrated circuits

A memory includes a supply voltage generation circuit for providing a supply voltage to a plurality of SRAM cells of the memory during at least one mode of memory operation. The supply voltage generation circuit includes a first reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The first reference generation circuit provides a first voltage during an at least one mode of memory operation. The supply voltage generation circuit includes a second reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The second reference generation circuit provides a second voltage during the at least one mode of memory operation. The voltage generation circuit includes an output for providing a supply voltage to the plurality of cells during the at least one mode of memory operation.

Voltage generation circuit for SRAM

A system includes test control circuitry and a memory. The memory includes a memory array, a pre-decode circuit, and a plurality of address latches. Each address latch of the plurality of address latches is configured to operate in a scan chain of a plurality of scan chains for scan testing. A first set of the plurality of address latches each has a data input coupled to a corresponding address pin of the first memory and each has an output coupled to the pre-decode circuit. A second set of the plurality of address latches, mutually exclusive of the first set, each has a data input coupled to a data input of at least one latch in the first set of the plurality of latches and each is configured to not provide any input to the pre-decode circuit.

Integrated circuit having test circuitry for memory sub-systems

A physically unclonable function (PUF) includes an array of differential PUF bits arranged in rows and columns, wherein each differential bit is located at an intersection of a row and a column, and includes a first PUF cell coupled to a corresponding first bit line and first source line and a second PUF cell coupled to a corresponding second bit line and second source line. The PUF includes a source bias transistor coupled between each corresponding first source line and a first power supply terminal and between each corresponding second source line and the first power supply terminal, wherein a gate electrode of each of the source bias transistors is coupled to a second power supply terminal, and a corresponding set of margin transistors coupled in parallel with each source bias transistor, wherein a gate electrode of each margin transistor is coupled to receive a corresponding margin setting control signal.

Physically unclonable function having source bias transistors

A data processing system and method for generating a digital code for use as a physically unclonable function (PUF) response is provided. The method includes activating a plurality of word lines for a read operation. A first bit line is coupled to a first input of a comparator during the read operation. A second bit line is coupled to a second input of the comparator during the read operation. A current is generated on each of the first and second bit lines. The currents on the first and second bit lines are converted to voltages. The voltage on the first bit line is compared to the voltage on the second bit line. A logic bit is output from the comparator as part of the digital code, a logic state of the logic bit is determined in response to the comparison. By selecting multiple word lines to determine a PUF response, noise immunity is improved.

Data processing system and method for generating a digital code with a physically unclonable function

A physically unclonable function (PUF) is implemented using a PUF array of single-transistor cells organized as a plurality of word lines and intersecting bit lines. A single-transistor cell is connected to a word line and bit line at each of the intersections. A current source is coupled to each of the bit lines and provides a current when a PUF cell connected to the bit line is conductive. The bit lines are organized in pairs. A PUF evaluation engine is coupled to the PUF array and provides an address for selecting a word line of the PUF array in response to a challenge. A comparator is coupled to each pair of bit lines of the PUF array for detecting a current. The comparator provides a voltage signal in response to detecting a difference current between the first and second bit line. The PUF evaluation engine receives the voltage signal and generates a logic bit.

Physically unclonable function and method for generating a digital code

A memory system includes an isolated first well of a first polarity and an array of volatile memory cells. Each of the memory cells includes a first set of transistors in the isolated first well, and a second set of transistors. A source bias circuit is coupled to the array of volatile memory cells. At least a portion of the source bias circuit is in the isolated first well and coupled to source electrodes of the first set of transistors of each of the memory cells. A control circuit is configured to enable the source bias circuit.

Memory system having a source bias circuit

A scan circuit and methods of operating a scan circuit are provided. The method for operating a scan circuit includes providing a first scan flip-flop which includes an overwrite feature. With the overwrite feature enabled, a change in functional behavior of the first scan flip-flop occurs based on a control signal. The method may further include capturing data at a first input of the first scan flip-flop during a first state of the control signal and resetting captured data by using the overwrite feature during a first transition of the control signal. The method may further include forming a scan chain with one or more of the first scan flip-flops and one or more second scan flip-flops. The second scan flip-flops may include a similar overwrite feature, having the overwrite feature disabled.

Data processing system with built-in self-test and method therefor

A method of programming a memory includes selecting a logic state for programming a first bitcell of the memory. A first one-time-programmable (OTP) element of the first bitcell is programmed using a first set of conditions intended to achieve a first target resistance in accordance with the selected logic state which results in a first degree of programming of the first OTP element. A second OTP element of the first bitcell is programmed using a second set of conditions different from the first set of conditions intended to achieve a second target resistance in accordance with the selected logic state which results in a second degree of programming of the second OTP element, wherein the first and second degrees of programming are visually indistinguishable.

Memory having one time programmable (OTP) elements and a method of programming the memory

A physically unclonable function (PUF) is implemented in a plurality of SRAM cells. In a method for generating a PUF response, a logic zero is first written to all the SRAM cells of the PUF. A bit line coupled to the storage node that stores the logic zero of each SRAM cell is biased to a predetermined voltage. The bit lines are then selected for an evaluation read operation. During the evaluation read, a read current of one of the bit lines from one column is converted to a first voltage and a read current of another bit line of another column is converted to a second voltage. The first voltage is then compared to the second voltage. A logic state of a bit of the PUF response is determined as a result of the comparison. The logic bit may be provided to the input of a parallel-in serial-out shift register. There may be a comparator for each logic bit, or a few comparators may be shared between the logic bits. The PUF response may be used to provide a signature for the data processing system. The back-bias of each cell may be selectively adjusted.

SRAM based physically unclonable function and method for generating a PUF response

A circuit includes a first driver to provide a first driver signal at an output. The first driver signal corresponds to a voltage operatively coupled to a VSS terminal of the first driver when driving a logic low. A first capacitor includes a first terminal coupled to the VSS terminal of the first driver. A boost circuit includes a first input coupled to the output of the first driver and a first output coupled to a second terminal of the first capacitor. The boost circuit is configured to cause the first capacitor to provide a boosted voltage at the VSS terminal.

Write assist circuit and method therefor

A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.

Low swing flip-flop with reduced leakage slave latch

A driver circuit having an adjustable output signal includes a logic circuit configured to receive an input signal into a first input terminal and an output circuit coupled to the logic circuit, wherein the output circuit is configured to generate, at an output terminal of the output circuit, an output signal having a signal level that changes in response to a signal level of the input signal. The driver circuit further includes a feedback circuit coupled to a second input terminal of the logic circuit. The feedback circuit includes first and second gate terminals coupled to the output terminal and a third gate terminal coupled to a control signal supply, wherein the feedback circuit is configured to control a maximum level of the output signal from the driver circuit based on an operating threshold of the feedback circuit as set by a control signal generated by the control signal supply.

Method and apparatus for a tunable driver circuit

A semiconductor memory device and method of operation are provided for a multi-bank memory array () with an address fault detector circuit () connected to split word lines (WLn-WLm) across multiple banks, where the address fault detector circuit includes at least a first MOSFET transistor (-) connected to each word line for detecting an error-free operation mode and a plurality of different transient address faults including a 'no word line select,' 'false word line select,' and &#x201c;multiple word line select&#x201d; failure mode at one of the first and second memory banks. In selected embodiments, the address fault detector provides resistive coupling (-) between split word lines across multiple banks to create interaction or contention between split word lines to create a unique voltage level on a fault detection bit line during an address fault depending on the fault type.

Address fault detection circuit

A CMOS cell incorporated on an integrated circuit including a PMOS transistor and an NMOS transistor. The current terminals of the PMOS and NMOS transistors are coupled in series between a lower voltage supply rail and a reference rail. The well connection of the PMOS transistor is coupled to an upper voltage supply rail having a voltage level greater than the lower voltage supply rail. The CMOS cell has low voltage swing and low leakage current to reduce power consumption. A second PMOS and NMOS transistor pair may be included and coupled in similar manner and to the first PMOS and NMOS pair to form a non-inverting cell. The PMOS transistors may be implemented in an N-well that is conductively tied to the upper supply voltage rail to avoid isolation barriers. The cell may be used in a clock tree to significantly reduce power consumption of the integrated circuit.

Low leakage CMOS cell with low voltage swing

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Austin, TX, United States of America

Alexander Hoefler