National Semiconductor Corporation

Lsi Logic Corporation

Sprague Electric Company

Solid State Scientific Corporation

Allegro Microsystems, LLC

Other

Texas Instruments Corporation

Alexander H Owens

David S Pan

Mark A Halfacre

Shahin Toutounchi

Wing K Huie

Abraham Fong Yee

Ashok S Prabhu

Shaw Wei Lee

Sadanand R Patil

Brian K Rosier

David Tsuei

Michael Lyu

Kanak C Sarma

Peter J Hopper

Albert M Bergemont

Peter B Johnson

Yuri Mirgorodski

Gobi R Padmanabhan

Philippe Schoenborn

Andy Strachan

Douglas Brisbin

Pamela Shiell Trammel

Ting P Yen

Michael J Zunino

Mike Lyu

Chin Miin Shyu

A semiconductor apparatus includes a first substrate and a second substrate located over a first portion of the first substrate and separated from the first substrate by a buried layer. The semiconductor apparatus also includes an epitaxial layer located over a second portion of the first substrate and isolated from the second substrate. The semiconductor apparatus further includes a first transistor formed at least partially in the second substrate and a second transistor formed at least partially in or over the epitaxial layer. The second substrate and the epitaxial layer have bulk properties with different electron and hole mobilities. At least one of the transistors is configured to receive one or more signals of at least about 5V. The first substrate could have a first crystalline orientation, and the second substrate could have a second crystalline orientation.

Method for improved mobility using hybrid orientation technology (HOT) in conjunction with selective epitaxy and related apparatus

Method for using hybrid orientation technology (HOT) in conjunction with selective epitaxy to form semiconductor devices with regions of different electron and hole mobilities and related apparatus

A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and a notch region along the edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The second surface of the semiconductor substrate includes a bottom protective layer with electrical connectors. The surface portion of the top protective layer includes electrical contact pads that are electrically interconnected with electrical contact pad extensions. The electrical contact pad extensions are interconnected with electrical connectors via a backside electrical connector that overlaps the electrical contact pad extensions forming a lap connection. Methods for constructing such devices and connections are also disclosed.

Electrical die contact structure and fabrication method

An LDMOS structure which provides for reduced hot carrier effects. The reduction in hot carrier effects is achieved by increasing the size of the drain region of the LDMOS relative to the size of the source region. The larger size of the drain region reduces the concentration of electrons entering the drain region. This reduction in the concentration of electrons reduces the number of impact ionizations, which in turn reduces the hot carrier effects. The overall performance of the LDMOS is improved by reducing the hot carrier effects.

LDMOS transistor structure for improving hot carrier reliability

A method for making an electrically programmable and erasable memory cell is disclosed. Specifically, a method for creating a floating gate using shallow trench isolation-type techniques is utilized to provide a floating gate having sharply defined tip characteristics. A first insulating layer is formed over a substrate. A conductive material is formed over the first insulating layer. A trench is defined in the conductive layer. This trench is filled with an oxide which is used as a mask to define tips of the floating gate during an etching process which defines the edges of the floating gate. After the floating gate has been etched, a tunneling oxide deposited over the floating gate. A conductive material is then formed over the tunneling oxide.

Method of using trenching techniques to make a transistor with a floating gate

A method of forming a localized oxidation having reduced bird's beak encroachment in a semiconductor device by providing an opening in the silicon substrate that has sloped sidewalls with a taper between about 10&deg; and about 75&deg; as measured from the vertical axis of the recess opening and then growing field oxide within the tapered recess opening for forming the localized oxidation.

Method of forming local oxidation with sloped silicon recess

A trench is etched in a silicon substrate covered with an oxide/nitride stack and a field oxide layer is then grown through oxidation of the silicon in the substrate such that the trench is partly filled. There is reduced oxide encroachment into the active areas under the nitride layer because of the partial field oxide growth. Double oxide layers are deposited over the surface of the field oxide layer and the oxide/nitride stack such that the oxide layers fill the remainder of the trench and produce a nearly planar topology. The double oxide layers are then etched back to the nitride layer through chemical mechanical polishing, leaving the field isolation region. After stripping the oxide/nitride stack, a gate oxide layer is grown. A minimal amount of oxide is required to fill the trench because the trench is already almost filled with the field oxide layer and because of the shallow depth of the trench. Consequently, the etch back step causes minimal dishing. Further, the field oxide layer rounds the corner between the trench and the active area, obviating the need for a thin oxide liner in the trench.

Modified recessed locos isolation process for deep sub-micron device

An improved MOS-type integrated circuit structure, and a method of making same, are described wherein a diode is electrically connected between the polysilicon gate electrode and the semiconductor substrate, and physically located in the substrate below the contact area of the polysilicon gate electrode so that no extra lateral space is needed to provide such a diode connection between the polysilicon gate electrode and the substrate. The junction is formed in the substrate in a region where the contact area of the gate electrode is usually positioned over field oxide. An opening is provided for the diode in the field oxide region of the substrate, by masking off an additional portion of the substrate, when the field oxide is initially grown, to provide for location of the diode therein.

Method of forming an MOS-type integrated circuit structure with a diode

A semiconductor integrated circuit includes a semiconductor circuit chip housed in a package. The package provides for electrical interface of the integrated circuit chip with external circuitry, and also provides environmental protection for the circuit chip. The circuit chip includes a circuit portion which liberates heat into the semiconductor substrate of the chip during operation of the integrated circuit. The integrated circuit chip also includes a layer of insulative material which overlies the semiconductor substrate. A thermally conductive plug member penetrates through the layer of insulative material and extends into a hole formed in the semiconductor substrate. This plug member is in conductive heat transfer relation with the material of the semiconductor substrate, and connects thermally with high-conductivity heat transfer structure conducting heat from the substrate to the package for liberation to the ambient.

High density CMOS integrated circuit with heat transfer structure for

A multilevel gate array MOS-type integrated circuit structure is described wherein each source, drain, and gate electrode region in the integrated circuit structure is accessible directly through a contact opening formed normal to the plane of the underlying substrate through an overlying insulation layer. The multilevel gate array MOS-type integrated circuit structure of the invention comprises a substrate; a first semiconductor device level comprising one or more first source regions, one or more first drain regions, and one or more first gate electrode regions; and a second semiconductor device level formed over the first semiconductor device level and comprising one or more second source regions arranged to permit access, normal to the plane of the underlying substrate, to an underlying first source region in the first level, one or more second drain regions arranged to permit access, normal to the plane of the underlying substrate, to an underlying drain region in the first level, and one or more second gate electrode regions arranged to permit access, normal to the plane of the underlying substrate, to an underlying gate electrode region in the first level; whereby contact openings may be formed, normal to the plane of the substrate, to each of the source, drain, and gate electrode regions in both semiconductor device levels.

Multilevel gate array integrated circuit structure with perpendicular

A CMOS integrated circuit structure is disclosed having a patterned nitride passivation layer, wherein the nitride is patterned such that it does not overlie the thin gate oxide portions of one or more of the MOS devices. When protection against the effects of external radiation is desired, the thin gate oxide areas of the PMOS devices are left uncovered by the patterned nitride passivation layer. When protection is desired against the effects of internally generated 'hot electrons', the thin gate oxide areas of the NMOS devices are left uncovered by the patterned nitride passivation layer.

Integrated circuit structure including CMOS devices protected by

A technique for improving the radiation hardness and hot-electron resistance of a CMOS integrated circuit is described whereby undesirable hydrogen ions may be vented through any holes, such as contact holes, in an overlying passivation layer by applying an elevated temperature and/or electrical bias to the integrated circuit die. The elevated temperature and electrical bias serve to accelerate the process by which hydrogen vents from the die. The elimination of unwanted hydrogen significantly reduces threshold shifts in the CMOS integrated circuit, providing greater radiation hardness and hot-electron resistance.

High-temperature bias anneal of integrated circuits for improved

A radiation hardened NMOS transistor structure suited for application to radiation hardened CMOS devices, and the method for manufacturing it is disclosed. The new transistor structure is characterized by 'P' doped guard bands running along and immediately underlying the two bird's beak regions perpendicular to the gate. The transistor and the CMOS structure incorporating it exhibit speed and size comparable to those of conventional non-rad-hard CMOS structure, relatively simple manufacturing, and excellent total-dose radiation hardness.

Radiation hardened CMOS structure using an implanted P guard structure

A vertical NPN transistor is fabricated in a silicon integrated circuit substrate growing an N-type epitaxial layer, forming a preliminary P-type base region in the surface of the epitaxial layer, covering the surface with a protective glass layer, selectively etching a hole in the glass layer at an emitter-designated place over the preliminary base region, depositing N-type impurities through the hole into the silicon surface to become the emitter, implanting P-type impurities, of a kind that diffuse faster than the N-type impurities, through the hole into the epitaxial layer and heating to at least anneal the substrate. The hole is then filled to provide electrical contact to the emitter.

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Los Gatos, CA, United States of America

Alexander H Owens