Spansion Llc.

Advanced Micro Devices Corporation

Koninklijke Philips Corporation N.v.

Lumileds LLC

Other

Globalfoundries Inc.

Cypress Semiconductor Corporation

Lumileds Holding B.v.

Spansion LLC Advanced Micro Devices, Inc

Advanced Micro Devices, Inc. and Spansion LLC

Alexander H Nickel

Minh Quoc Tran

Jipu Lei

Stefano Schiaffino

Hieu T Pham

Minh-Van Ngo

Sergey D Lopatin

Minh Van Ngo

Lu You

Hirokazu Tokuno

Erik Wilson

Angela Tai Hui

Shenqing Fang

Robert A Huertas

Sung Jin Kim

Fei Wang

Daniel Alexander Steigerwald

Yajun Wei

Salman Akram

Scott Allan Bell

Calvin T Gabriel

Suzette Keefe Pangrle

Mark S Chang

Grigoriy Basin

Chun Chen

Kashmir S Sahota

Igor Sokolik

Jihwan Choi

Phillip Lawrence Jones

Wai Lo

Gang Xue

Zubin Patel

Mooi Guan Ng

Jeong-Uk Huh

Masato Tsuboi

Shinich Imada

Steven C Avanzino

Jeffrey Allan Shields

Simon S Chan

Oleg Borisovich Shchekin

William S Brennan

Ning Cheng

Jean Y Yang

Paul L King

Richard Paul Kingsborough

Juri Krieger

Kuochou Tai

Jeffrey Dellert Kmetec

Inkuk Kang

Swaroop Kaza

Wen Yu

Christopher Lee Pike

Joffre F Bernard

Stuart Spitzer

Pei-Yuan Gao

Weidong Qian

Allen Lewis Evans

David Gaun

Franklin Joseph Wall

Mohiuddin Mala

Amir Hossein Jafarpour

Robert Zona

Stefano Schiafino

Light emitting die () comprising a plurality of light emitting elements (310A, 310B), each having a pair of bond pads (NPand NP), wherein at least two diagonally opposite bond pads of adjacent light emitting elements on a die have their facing corners truncated () to enable a direct diagonal coupling of a complementary pair of diagonally opposite bond pads when the die is monted on a substrate on which an interconnection pattern is formed. By enabling diagonal as well as lateral coupling of the bond pads of multiple light emitting elements of a die, the multiple light emitting elements may be arranged in a variety of series and/or parallel configurations, thereby facilitating the use of the same die at different nominal operating voltages with a single interconnect layer on the substrate upon which the die is mounted.

Die bond pad design to enable different electrical configurations

A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer is formed in the gap followed by filling the gap with a metal. The metal is patterned to form stud bumps that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.

P&#x2014;N separation metal fill for flip chip LEDs

A method according embodiments of the invention includes providing a wafer of semiconductor devices. The wafer of semiconductor devices includes a semiconductor structure comprising a light emitting layer sandwiched between an n-type region and a p-type region. The wafer of semiconductor devices further includes first and second metal contacts for each semiconductor device. Each first metal contact is in direct contact with the n-type region and each second metal contact is in direct contact with the p-type region. The method further includes forming a structure that seals the semiconductor structure of each semiconductor device. The wafer of semiconductor devices is attached to a wafer of support substrates.

Sealed semiconductor light emitting device

A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.

Reducing solder pad topology differences by planarization

P-n separation metal fill for flip chip LEDs

A method according to embodiments of the invention includes providing a wafer comprising a semiconductor structure grown on a growth substrate. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region. The wafer includes trenches defining individual semiconductor devices. The trenches extend through an entire thickness of the semiconductor structure to reveal the growth substrate. The method further includes forming a thick conductive layer on the semiconductor structure. The thick conductive layer is configured to support the semiconductor structure when the growth substrate is removed. The method further includes removing the growth substrate.

Method of separating a wafer of semiconductor devices

A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region and first and second metal contacts, wherein the first metal contact is in direct contact with the n-type region and the second metal contact is in direct contact with the p-type region. First and second metal layers are disposed on the first and second metal contacts, respectively. The first and second metal layers are sufficiently thick to mechanically support the semiconductor structure. A sidewall of one of the first and second metal layers comprises a three-dimensional feature.

Semiconductor light emitting device with thick metal layers

The present claimed subject matter is directed to memory device that includes substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric.

Electrically programmable and eraseable memory device

Thick metal pillars are formed upon light emitting dies while the dies are still on their supporting wafer. A molding compound is applied to fill the space between the pillars on each die, and contact pads are formed atop the pillars. The metal pillars provide electrical contact between the contact pads and the electrical contacts of each light emitting die. The metal pillars maybe formed upon an upper metal layer of each die, and this upper metal layer maybe patterned to provide connections to individual elements within the die.

Chip scale light emitting device with metal pillars in a molding compound formed at wafer level

A light emitting diode (LED) structure () has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer () is formed in the gap followed by filling the gap with a metal (). The metal is patterned to form stud bumps () that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.

P-N separation metal fill for flip chip LEDs

An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.

High ultraviolet light absorbance silicon oxynitride film for improved flash memory device performance

The present memory device includes a substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. A method for fabricating such a memory device is also provided, including various approaches for forming the silicon oxynitride.

Electrically programmable and erasable memory device and method of fabrication thereof

During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 &#x212b; to about 500 &#x212b;, curing after deposition, as by UV radiation or by heating at a temperature of about 400&#xb0; C. to about 1000&#xb0; C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

Gap-filling with uniform properties

Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

Methods for forming a memory cell having a top oxide spacer

Growing community of inventors

Mountain View, CA, United States of America

Alexander H Nickel