Intel Corporation

Alexander Gendler

Ankush Varma

Larisa Novakovsky

Ariel Szapiro

Efraim Rotem

Krishnakanth Venkata Sistla

Nir Rosenzweig

Michael Mishaeli

Ashish V Choubal

Eliezer Weissmann

Nadav Shulman

Gavri Berger

Lev Makovsky

Arye Albahari

Elkana Korem

Doron Rajwan

Dean A Mulla

Igor Yanover

Nimrod Angel

Ido Melamed

Ariel Sabba

Niv Tokman

Nasser A Kurd

Vivek Garg

Tsvika Kurts

Yoni Aizik

Praveen Mosalikanti

Ruchira Sasanka

Kosta Luria

Arik Gihon

Adwait Purandare

Arkady Bramnik

Udi Sherel

Ohad Nachshon

Edo Hachamo

Hanan Shomroni

Paul S Diefenbaugh

Barnes Cooper

Guy M Therien

Joseph Nuzman

George Leifman

Yevgeni Sabin

Sagi Meller

Ameya Ambardekar

Gilad Cohen

Haim Granot

Nir Tell

Shmuel Zobel

Tamir Salus

Rachid Rayess

Robert Valentine

Ohad Falik

Avinash N Ananthakrishnan

Ittai Anati

Inder M Sodhi

Julius Yuli Mandelblat

Alexander Lyakhov

Tal Kuzi

Hisham Abu Salah

Esfir Natanzon

Lihu Rappoport

Tod F Schiff

Eric J DeHaemer

Alexander Uan-Zo-Li

Ian M Steiner

Ofer Levy

Michael Behar

Hisham Shafi

Ernest Knoll

Nikhil Gupta

Guy G Sotomayor

Israel Diamand

Arvind Raman

Sapumal Wijeratne

Inbar Weintrob

Ariel Berkovits

Nazar Syed Haider

Moty Mehalel

Vishwesh M Rudramuni

Roni Rosner

Ofer J Nathan

Erik Hallnor

Yair Talker

David Hunt

Zigi Walter

Rahul Agrawal

Yiftach Gilad

Suresh Chemudupati

Kimberly C Weier

Krishnamurthy Jambur Sathyanarayana

Hanna Alam

Eric Dehaemer

Shadi T Khasawneh

Chen Ranel

Eyal Hadas

Nir Misgav

Madhusudan Chidambaram

Oz Shitrit

Edward Brazil

In an embodiment, a processor may include a core domain comprising a plurality of processing cores, an uncore domain comprising an internal network, and a processor power management circuit. The processor power management circuit may be to: receive scalability hint values from the processing cores; determine a total core gain and a total uncore gain based at least in part on the scalability hint values; and distribute a frequency budget between the core domain and the uncore domain based at least in part on the total core gain and the total uncore gain. Other embodiments are described and claimed.

Distribution of frequency budget in a processor

In one embodiment, a processor includes: at least one configuration register to store configuration information for a hardware resource including a control circuit to configure the hardware resource based at least in part on the configuration information; a performance monitor to maintain performance information during execution of an application on the processor; and a controller coupled to the at least one configuration register. The controller may dynamically provide the configuration information to the at least one configuration register based at least in part on the performance information, and the control circuit is to adjust a performance tuning of the hardware resource according to the configuration information. Other embodiments are described and claimed.

System, apparatus and method for dynamically configuring one or more hardware resources of a processor

Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

Current control for a multicore processor

An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.

Frequency overshoot and voltage droop mitigation apparatus and method

A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.

Hardware-assisted core frequency and voltage scaling in a poll mode idle loop

An adaptive or dynamic power virus control scheme (hardware and/or software) that dynamically adjusts maximum dynamic capacitance (CdynMax) and corresponding maximum frequency (P0nMax) setting per application executed on a processor core. A power management unit monitors telemetry such as a number of throttled cycles due to CdynMax threshold excursions cycles for the processor core and a cost of average cycle Cdyn cost for the processor core. As the number of throttling cycles increases for the processor core, the aCode firmware of the power management unit decides to increase the Cdyn level or threshold for that core (e.g., to make the threshold less aggressive). As the average Cdyn cost over a number of cycles becomes lower than a threshold, aCode adjusts the threshold to a lower threshold (e.g., more aggressive threshold) and lower Cdyn.

Apparatus and method to detect power supply security attack and risk mitigation

An apparatus and method for intelligent power virus protection in a processor. For example, one embodiment of a processor comprises: first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction; detection circuitry to detect one or more instructions of a particular type and/or width; evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry when executing the one or more instructions based on the detected instruction types and/or widths; and control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.

Apparatus and method for power virus protection in a processor

A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

Power control arbitration

In one embodiment, an apparatus comprises: a plurality of intellectual property (IP) circuits, each of the plurality of IP circuits including a configuration register to store a dynamic current budget; and a power controller coupled to the plurality of IP circuits, the power controller including a dynamic current sharing control circuit to receive current throttling hint information regarding a workload to be executed on at least some of the plurality of IP circuits and generate the dynamic current budget for each of the plurality of IP circuits based at least in part thereon. Other embodiments are described and claimed.

System, apparatus and method for dynamically controlling current consumption of processing circuits of a processor

In one embodiment, a processor includes a current protection controller to: receive instruction width information and instruction type information associated with one or more instructions stored in an instruction queue prior to execution of the one or more instructions by an execution circuit; determine a power license level for the core based on the corresponding instruction width information and the instruction type information; generate a request for a license for the core corresponding to the power license level; and communicate the request to a power controller when the one or more instructions are non-speculative, and defer communication of the request when at least one of the one or more instructions is speculative. Other embodiments are described and claimed.

System, apparatus and method for power license control of a processor

In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

Adjusting a throttling threshold in a processor

Methods and apparatus relating to techniques for processor core energy management are described. In an embodiment, energy management logic causes a modification to energy consumption by an electrical load (such as a processor core) based at least in part on comparison of an electrical current value and an operating current threshold value. The electrical current value is detected at an electrical current sensor coupled to the electrical load. Other embodiments are also disclosed and claimed.

Processor core energy management

Growing community of inventors

Kiriat Motzkin, Israel

Alexander Gendler